-from openpower.decoder.power_enums import XER_bits
-
-
-class State:
- def get_state(self):
- yield from self.get_intregs()
- yield from self.get_crregs()
- yield from self.get_xregs()
- yield from self.get_pc()
-
- def compare(self, s2):
- # Compare int registers
- for i, (self.intregs, s2.intregs) in enumerate(
- zip(self.intregs, s2.intregs)):
- print("asserting...reg", i, self.intregs, s2.intregs)
- print("code, frepr(code)", self.code, repr(self.code))
- self.dut.assertEqual(self.intregs, s2.intregs,
- "int reg %d (%s) not equal (%s) %s. got %x expected %x" %
- (i, self.state_type, s2.state_type, repr(self.code),
- self.intregs, s2.intregs))
-
- # CR registers
- for i, (self.crregs, s2.crregs) in enumerate(
- zip(self.crregs, s2.crregs)):
- print("asserting...cr", i, self.crregs, s2.crregs)
- self.dut.assertEqual(self.crregs, s2.crregs,
- "cr reg %d (%s) not equal (%s) %s. got %x expected %x" %
- (i, self.state_type, s2.state_type, repr(self.code),
- self.crregs, s2.crregs))
+""" Power ISA test API
- # XER
- self.dut.assertEqual(self.so, s2.so, "so mismatch (%s != %s) %s" %
- (self.state_type, s2.state_type, repr(self.code)))
- self.dut.assertEqual(self.ov, s2.ov, "ov mismatch (%s != %s) %s" %
- (self.state_type, s2.state_type, repr(self.code)))
- self.dut.assertEqual(self.ca, s2.ca, "ca mismatch (%s != %s) %s" %
- (self.state_type, s2.state_type, repr(self.code)))
+This module implements the creation, inspection and comparison
+of test states for TestIssuer HDL
- # pc
- self.dut.assertEqual(self.pc, s2.pc, "pc mismatch (%s != %s) %s" %
- (self.state_type, s2.state_type, repr(self.code)))
+"""
+from openpower.decoder.power_enums import XER_bits
+from openpower.util import log
+from openpower.test.state import (State, state_add, state_factory,
+ TestState,)
+from soc.fu.compunits.test.test_compunit import get_l0_mem
-class SimState(State):
- def __init__(self, sim):
- self.sim = sim
+class HDLState(State):
+ """HDLState: Obtains registers and memory from an nmigen simulator
+ object by implementing State class methods.
+ """
+ def __init__(self, core):
+ super().__init__()
+ self.core = core
- def get_intregs(self):
+ def get_fpregs(self):
if False:
yield
- self.intregs = []
+ self.fpregs = []
for i in range(32):
- simregval = self.sim.gpr[i].asint()
- self.intregs.append(simregval)
- print("class sim int regs", list(map(hex, self.intregs)))
-
- def get_crregs(self):
- if False:
- yield
- self.crregs = []
- for i in range(8):
- cri = self.sim.crl[7 - i].get_range().value
- self.crregs.append(cri)
- print("class sim cr regs", list(map(hex, self.crregs)))
-
- def get_xregs(self):
- if False:
- yield
- self.xregs = []
- self.so = self.sim.spr['XER'][XER_bits['SO']].value
- self.ov = self.sim.spr['XER'][XER_bits['OV']].value
- self.ov32 = self.sim.spr['XER'][XER_bits['OV32']].value
- self.ca = self.sim.spr['XER'][XER_bits['CA']].value
- self.ca32 = self.sim.spr['XER'][XER_bits['CA32']].value
- self.ov = self.ov | (self.ov32 << 1)
- self.ca = self.ca | (self.ca32 << 1)
- self.xregs.extend((self.so, self.ov, self.ca))
- print("class sim xregs", list(map(hex, self.xregs)))
-
- def get_pc(self):
- if False:
- yield
- self.pcl = []
- self.pc = self.sim.pc.CIA.value
- self.pcl.append(self.pc)
- print("class sim pc", hex(self.pc))
-
-
-class HDLState(State):
- def __init__(self, core):
- self.core = core
+ self.fpregs.append(0)
def get_intregs(self):
self.intregs = []
else:
rval = yield self.core.regs.int.memory._array[i]
self.intregs.append(rval)
- print("class hdl int regs", list(map(hex, self.intregs)))
+ log("class hdl int regs", list(map(hex, self.intregs)))
def get_crregs(self):
self.crregs = []
for i in range(8):
- rval = yield self.core.regs.cr.regs[i].reg
+ rval = yield self.core.regs.cr.regs[7-i].reg
self.crregs.append(rval)
- print("class hdl cr regs", list(map(hex, self.crregs)))
+ log("class hdl cr regs", list(map(hex, self.crregs)))
def get_xregs(self):
self.xregs = []
self.ov = yield self.xr.regs[self.xr.OV].reg
self.ca = yield self.xr.regs[self.xr.CA].reg
self.xregs.extend((self.so, self.ov, self.ca))
- print("class hdl xregs", list(map(hex, self.xregs)))
+ log("class hdl xregs", list(map(hex, self.xregs)))
def get_pc(self):
self.pcl = []
self.state = self.core.regs.state
+ # relies on the state.r_port being permanently held as PC
self.pc = yield self.state.r_ports['cia'].o_data
self.pcl.append(self.pc)
- print("class hdl pc", hex(self.pc))
-
-
-global state_factory
-state_factory = {'sim': SimState, 'hdl': HDLState}
-
-
-def TestState(state_type, to_test, dut, code):
- state_class = state_factory[state_type]
- state = state_class(to_test)
- state.to_test = to_test
- state.dut = dut
- state.state_type = state_type
- state.code = code
- yield from state.get_state()
- return state
+ log("class hdl pc", hex(self.pc))
+
+ def get_mem(self):
+ self.mem = {}
+ # get the underlying HDL-simulated memory from the L0CacheBuffer
+ if hasattr(self.core, "icache"):
+ # err temporarily ignore memory
+ return # XXX have to work out how to deal with wb_get
+ hdlmem = get_l0_mem(self.core.l0)
+ for i in range(hdlmem.depth):
+ value = yield hdlmem._array[i] # should not really do this
+ self.mem[i*8] = value
+
+
+# add to State Factory
+state_add('hdl', HDLState)
projects / soc.git / blobdiff