tracked down byte-reversal in LDST ISACaller and LDSTCompUnit

[soc.git] / src / soc / simulator / test_sim.py

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index c6a212fd5c0062896a2e5dac78db936bf03f6979..63cb5d10327c22683e9423d4ec2f5ad901e53066 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -49,6 +49,34 @@ class GeneralTestCases(FHDLTestCase):
         super().__init__(name)
         self.test_name = name
 
+    @unittest.skip("disable")
+    def test_0_litex_bios_r1(self):
+        """litex bios IMM64 macro test
+        """
+        lst = [ "addis     1,0,0",
+                 "ori     1,1,0",
+                 "rldicr  1,1,32,31",
+                 "oris    1,1,256",
+                 "ori     1,1,3832",
+               ]
+        with Program(lst, bigendian) as program:
+            self.run_tst_program(program, [1], initial_mem={})
+
+    @unittest.skip("disable")
+    def test_0_litex_trampoline(self):
+        lst = ["tdi   0,0,0x48",
+               "b     0x28",
+               "mfmsr r11",
+               "bcl 20,31,4",
+               "mflr r10",
+               "addi r10,r10,20",
+               "mthsrr0 r10",
+               "mthsrr1 r11",
+               "hrfid",
+               ]
+        with Program(lst, bigendian) as program:
+            self.run_tst_program(program, [], initial_mem={})
+
     @unittest.skip("disable")
     def test_0_cmp(self):
         lst = ["addi 6, 0, 0x10",
@@ -68,7 +96,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3, 4])
 
-    @unittest.skip("disable")
+    #@unittest.skip("disable")
     def test_ldst(self):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
@@ -83,6 +111,21 @@ class GeneralTestCases(FHDLTestCase):
                                  [1, 2, 3],
                                  initial_mem)
 
+    #@unittest.skip("disable")
+    def test_ldst_update(self):
+        lst = ["addi 1, 0, 0x5678",
+               "addi 2, 0, 0x1234",
+               "stwu  1, 0(2)",
+               "lwz  3, 0(2)"
+               ]
+        initial_mem = {0x1230: (0x5432123412345678, 8),
+                       0x1238: (0xabcdef0187654321, 8),
+                       }
+        with Program(lst, bigendian) as program:
+            self.run_tst_program(program,
+                                 [1, 2, 3],
+                                 initial_mem)
+
     @unittest.skip("disable")
     def test_ld_rev_ext(self):
         lst = ["addi 1, 0, 0x5678",
@@ -103,7 +146,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
-    @unittest.skip("disable")
+    #@unittest.skip("disable")
     def test_ldst_extended(self):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
@@ -138,7 +181,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3, 4, 5])
 
-    @unittest.skip("disable")
+    #@unittest.skip("disable")
     def test_add_with_carry(self):
         lst = ["addi 1, 0, 5",
                "neg 1, 1",
@@ -203,6 +246,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3, 4], initial_mem)
 
+    @unittest.skip("disable")
     def test_nop(self):
         lst = ["addi 1, 0, 0x1004",
                "ori 0,0,0", # "preferred" form of nop
@@ -225,6 +269,7 @@ class GeneralTestCases(FHDLTestCase):
             program.assembly = '\n'.join(disassembly) + '\n' # XXX HACK!
             self.run_tst_program(program, [1, 3])
 
+    @unittest.skip("disable")
     def test_loop(self):
         """in godbolt.org:
         register unsigned long i asm ("r12");
@@ -243,6 +288,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [9], initial_mem={})
 
+    @unittest.skip("disable")
     def test_30_addis(self):
         lst = [  # "addi 0, 0, 5",
             "addis 12, 0, 0",
@@ -296,8 +342,7 @@ class DecoderBase:
                 yield Settle()
 
         sim.add_process(process)
-        with sim.write_vcd("simulator.vcd", "simulator.gtkw",
-                           traces=[]):
+        with sim.write_vcd("pdecode_simulator.vcd"):
             sim.run()
 
         return simulator