self.run_tst_program(program, [1])
def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
- initial_mem=None):
+ initial_mem=None):
initial_regs = [0] * 32
tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
- initial_mem, 0)
+ initial_mem, 0)
self.test_data.append(tc)
super().__init__(name)
self.test_name = name
+ @unittest.skip("disable")
+ def test_0_litex_bios_r1(self):
+ """litex bios IMM64 macro test
+ """
+ lst = [ "addis 1,0,0",
+ "ori 1,1,0",
+ "rldicr 1,1,32,31",
+ "oris 1,1,256",
+ "ori 1,1,3832",
+ ]
+ with Program(lst, bigendian) as program:
+ self.run_tst_program(program, [1], initial_mem={})
+
+ @unittest.skip("disable")
+ def test_0_litex_trampoline(self):
+ lst = ["tdi 0,0,0x48",
+ "b 0x28",
+ "mfmsr r11",
+ "bcl 20,31,4",
+ "mflr r10",
+ "addi r10,r10,20",
+ "mthsrr0 r10",
+ "mthsrr1 r11",
+ "hrfid",
+ ]
+ with Program(lst, bigendian) as program:
+ self.run_tst_program(program, [], initial_mem={})
+
@unittest.skip("disable")
def test_0_cmp(self):
lst = ["addi 6, 0, 0x10",
with Program(lst, bigendian) as program:
self.run_tst_program(program, [1, 2, 3, 4])
- @unittest.skip("disable")
+ #@unittest.skip("disable")
def test_ldst(self):
lst = ["addi 1, 0, 0x5678",
"addi 2, 0, 0x1234",
"stw 1, 0(2)",
"lwz 3, 0(2)"
- ]
+ ]
initial_mem = {0x1230: (0x5432123412345678, 8),
0x1238: (0xabcdef0187654321, 8),
- }
+ }
+ with Program(lst, bigendian) as program:
+ self.run_tst_program(program,
+ [1, 2, 3],
+ initial_mem)
+
+ #@unittest.skip("disable")
+ def test_ldst_update(self):
+ lst = ["addi 1, 0, 0x5678",
+ "addi 2, 0, 0x1234",
+ "stwu 1, 0(2)",
+ "lwz 3, 0(2)"
+ ]
+ initial_mem = {0x1230: (0x5432123412345678, 8),
+ 0x1238: (0xabcdef0187654321, 8),
+ }
with Program(lst, bigendian) as program:
self.run_tst_program(program,
[1, 2, 3],
with Program(lst, bigendian) as program:
self.run_tst_program(program, [1, 2, 3])
- @unittest.skip("disable")
+ #@unittest.skip("disable")
def test_ldst_extended(self):
lst = ["addi 1, 0, 0x5678",
"addi 2, 0, 0x1234",
with Program(lst, bigendian) as program:
self.run_tst_program(program, [1, 2, 3, 4, 5])
- @unittest.skip("disable")
+ #@unittest.skip("disable")
def test_add_with_carry(self):
lst = ["addi 1, 0, 5",
"neg 1, 1",
"addi 3, 0, 0x00ee",
"stb 3, 1(2)",
"lbz 4, 1(2)",
- ]
+ ]
initial_regs = [0] * 32
initial_regs[1] = 0x1004
initial_regs[2] = 0x1008
initial_mem = {0x1000: (0x5432123412345678, 8),
0x1008: (0xabcdef0187654321, 8),
0x1020: (0x1828384822324252, 8),
- }
+ }
with Program(lst, bigendian) as program:
- self.run_tst_program(program, [3,4], initial_mem)
+ self.run_tst_program(program, [3, 4], initial_mem)
@unittest.skip("disable")
def test_3_load_store(self):
initial_mem = {0x1000: (0x5432123412345678, 8),
0x1008: (0xabcdef0187654321, 8),
0x1020: (0x1828384822324252, 8),
- }
+ }
with Program(lst, bigendian) as program:
- self.run_tst_program(program, [1,2,3,4], initial_mem)
+ self.run_tst_program(program, [1, 2, 3, 4], initial_mem)
+ @unittest.skip("disable")
+ def test_nop(self):
+ lst = ["addi 1, 0, 0x1004",
+ "ori 0,0,0", # "preferred" form of nop
+ "addi 3, 0, 0x15eb",
+ ]
+ initial_regs = [0] * 32
+ with Program(lst, bigendian) as program:
+ self.run_tst_program(program, [1, 3])
+
+ @unittest.skip("disable")
+ def test_zero_illegal(self):
+ lst = bytes([0x10,0x00,0x20,0x39,
+ 0x0,0x0,0x0,0x0,
+ 0x0,0x0,0x0,0x0 ])
+ disassembly = ["addi 9, 0, 0x10",
+ "nop", # not quite
+ "nop"] # not quite
+ initial_regs = [0] * 32
+ with Program(lst, bigendian) as program:
+ program.assembly = '\n'.join(disassembly) + '\n' # XXX HACK!
+ self.run_tst_program(program, [1, 3])
+
+ @unittest.skip("disable")
def test_loop(self):
"""in godbolt.org:
register unsigned long i asm ("r12");
} while (i != 0);
}
"""
- lst = ["addi 9, 0, 0x10", # i = 16
+ lst = ["addi 9, 0, 0x10", # i = 16
"addi 9,9,-1", # i = i - 1
"cmpi 0,1,9,12", # compare 9 to value 0, store in CR2
"bc 4,0,-8" # branch if CR2 "test was != 0"
with Program(lst, bigendian) as program:
self.run_tst_program(program, [9], initial_mem={})
+ @unittest.skip("disable")
def test_30_addis(self):
- lst = [#"addi 0, 0, 5",
- "addis 12, 0, 0",
- ]
+ lst = [ # "addi 0, 0, 5",
+ "addis 12, 0, 0",
+ ]
with Program(lst, bigendian) as program:
self.run_tst_program(program, [12])
def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
- initial_mem=None):
+ initial_mem=None):
initial_regs = [0] * 32
tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
- initial_mem, 0)
+ initial_mem, 0)
self.test_data.append(tc)
sim = Simulator(m)
def process():
- #yield pdecode2.dec.bigendian.eq(bigendian)
+ # yield pdecode2.dec.bigendian.eq(bigendian)
yield Settle()
while True:
try:
yield from simulator.setup_one()
- except KeyError: # indicates instruction not in imem: stop
+ except KeyError: # indicates instruction not in imem: stop
break
yield Settle()
yield from simulator.execute_one()
yield Settle()
-
sim.add_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
- traces=[]):
+ with sim.write_vcd("pdecode_simulator.vcd"):
sim.run()
return simulator
def run_tst_program(self, prog, reglist, initial_mem=None,
- extra_break_addr=None):
+ extra_break_addr=None):
import sys
simulator = self.run_tst(prog, initial_mem=initial_mem,
initial_pc=0x20000000)
print(simulator.gpr.dump())
def qemu_mem_compare(self, sim, qemu, check=True):
- if False: # disable convenient large interesting debugging memory dump
+ if False: # disable convenient large interesting debugging memory dump
addr = 0x0
qmemdump = qemu.get_mem(addr, 2048)
for i in range(len(qmemdump)):
s = hex(int(qmemdump[i]))
- print ("qemu mem %06x %s" % (addr+i*8, s))
+ print("qemu mem %06x %s" % (addr+i*8, s))
for k, v in sim.mem.mem.items():
qmemdump = qemu.get_mem(k*8, 8)
s = hex(int(qmemdump[0]))[2:]
- print ("qemu mem %06x %16s" % (k*8, s))
+ print("qemu mem %06x %16s" % (k*8, s))
for k, v in sim.mem.mem.items():
- print ("sim mem %06x %016x" % (k*8, v))
+ print("sim mem %06x %016x" % (k*8, v))
if not check:
return
for k, v in sim.mem.mem.items():
projects / soc.git / blobdiff