remove "sv." and replace with "sv" in all SVP64Asm

[soc.git] / src / soc / sv / trans / svp64.py

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index 21182295e3874df6977f51c00b38fd18ebd45f97..77745001dd44b6d292ff2c1b393009fb8de244f1 100644 (file)
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -614,21 +614,21 @@ class SVP64Asm:
 if __name__ == '__main__':
     lst = ['slw 3, 1, 4',
                  'extsw 5, 3',
-                 'sv.extsw 5, 3',
-                 'sv.cmpi 5, 1, 3, 2',
-                 'sv.setb 5, 31',
-                 'sv.isel 64.v, 3, 2, 65.v',
-                 'sv.setb/m=r3/sm=1<<r3 5, 31',
-                 'sv.setb/vec2 5, 31',
-                 'sv.setb/sw=8/ew=16 5, 31',
-                 'sv.extsw./ff=eq 5, 31',
-                 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
-                 'sv.extsw./pr=eq 5.v, 31',
-                 'sv.add. 5.v, 2.v, 1.v',
+                 'svextsw 5, 3',
+                 'svcmpi 5, 1, 3, 2',
+                 'svsetb 5, 31',
+                 'svisel 64.v, 3, 2, 65.v',
+                 'svsetb/m=r3/sm=1<<r3 5, 31',
+                 'svsetb/vec2 5, 31',
+                 'svsetb/sw=8/ew=16 5, 31',
+                 'svextsw./ff=eq 5, 31',
+                 'svextsw./satu/sz/dz/sm=r3/m=r3 5, 31',
+                 'svextsw./pr=eq 5.v, 31',
+                 'svadd. 5.v, 2.v, 1.v',
                 ]
     lst += [
-                 'sv.stw 5.v, 4(1.v)',
-                 'sv.ld 5.v, 4(1.v)',
+                 'svstw 5.v, 4(1.v)',
+                 'svld 5.v, 4(1.v)',
                  'setvl. 2, 3, 4, 1, 1',
           ]
     isa = SVP64Asm(lst)