changing svp64 asm syntax to use / instead of . as separators

[soc.git] / src / soc / sv / trans / svp64.py

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index a5dcf15ceae82ce37506ff1800775be474792e0c..0a9af5a6c65386def55e9b68f2a204ef7c868a3d 100644 (file)
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -169,14 +169,9 @@ class SVP64:
                 continue
             opcode = opcode[3:] # strip leading "sv."
 
-            # start working on decoding the svp64 op: sv.baseop/vec2.mode
-            opcode = opcode.split("/") # split at "/"
-            v30b_op = opcode[0]       # first is the v3.0B
-            if len(opcode) == 1:
-                opmodes = [] # no sv modes
-            else:
-                opmodes = opcode[1].split(".") # second splits by dots
-
+            # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
+            opmodes = opcode.split("/") # split at "/"
+            v30b_op = opmodes.pop(0)    # first is the v3.0B
             # check instruction ends with dot
             rc_mode = v30b_op.endswith('.')
             if rc_mode:
@@ -471,6 +466,17 @@ class SVP64:
                 elif encmode == 'svm': # sub-vector mode
                     mapreduce_svm = True
 
+            # sanity-check that 2Pred mask is same mode
+            if has_pmask and has_smask:
+                assert smmode == pmmode, \
+                    "predicate masks %s and %s must be same reg type" % \
+                        (pme, sme)
+
+            # sanity-check that twin-predication mask only specified in 2P mode
+            if ptype == '1P':
+                assert has_smask == False, \
+                    "source-mask can only be specified on Twin-predicate ops"
+
             # construct the mode field, doing sanity-checking along the way
 
             if mapreduce_svm:
@@ -540,19 +546,10 @@ class SVP64:
                     assert rc_mode, "pr-mode BO only possible when Rc=1"
                     mode |= (predresult << 2) # set BO
 
-            # whewww.... modes all done... :)
+            # whewww.... modes all done :)
+            # now put into svp64_rm
             mode |= sv_mode
-
-            # sanity-check that 2Pred mask is same mode
-            if has_pmask and has_smask:
-                assert smmode == pmmode, \
-                    "predicate masks %s and %s must be same reg type" % \
-                        (pme, sme)
-
-            # sanity-check that twin-predication mask only specified in 2P mode
-            if ptype == '1P':
-                assert has_smask == False, \
-                    "source-mask can only be specified on Twin-predicate ops"
+            svp64_rm |= (mode << 19) # mode: bits 19-23
 
             # put in predicate masks into svp64_rm
             if ptype == '2P':
@@ -596,11 +593,11 @@ if __name__ == '__main__':
                  'sv.cmpi 5, 1, 3, 2',
                  'sv.setb 5, 31',
                  'sv.isel 64.v, 3, 2, 65.v',
-                 'sv.setb/m=r3.sm=1<<r3 5, 31',
+                 'sv.setb/m=r3/sm=1<<r3 5, 31',
                  'sv.setb/vec2 5, 31',
-                 'sv.setb/sw=8.ew=16 5, 31',
+                 'sv.setb/sw=8/ew=16 5, 31',
                  'sv.extsw./ff=eq 5, 31',
-                 'sv.extsw./satu.sz.dz.sm=r3.m=r3 5, 31',
+                 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
                  'sv.extsw./pr=eq 5.v, 31',
                 ])
     csvs = SVP64RM()