move SVP64RM CSV class to new module

[soc.git] / src / soc / sv / trans / svp64.py

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index a5dcf15ceae82ce37506ff1800775be474792e0c..2e54f708580d6bcfd123c57a6403d14e7249c775 100644 (file)
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -18,7 +18,7 @@ import os, sys
 from collections import OrderedDict
 
 from soc.decoder.pseudo.pagereader import ISA
-from soc.decoder.power_enums import get_csv, find_wiki_dir
+from soc.decoder.power_svp64 import SVP64RM
 
 
 # identifies register by type
@@ -129,16 +129,6 @@ def decode_ffirst(encoding):
     return decode_bo(encoding)
 
 
-# gets SVP64 ReMap information
-class SVP64RM:
-    def __init__(self):
-        self.instrs = {}
-        pth = find_wiki_dir()
-        for fname in os.listdir(pth):
-            if fname.startswith("RM"):
-                for entry in get_csv(fname):
-                    self.instrs[entry['insn']] = entry
-
 
 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 class SVP64:
@@ -169,14 +159,9 @@ class SVP64:
                 continue
             opcode = opcode[3:] # strip leading "sv."
 
-            # start working on decoding the svp64 op: sv.baseop/vec2.mode
-            opcode = opcode.split("/") # split at "/"
-            v30b_op = opcode[0]       # first is the v3.0B
-            if len(opcode) == 1:
-                opmodes = [] # no sv modes
-            else:
-                opmodes = opcode[1].split(".") # second splits by dots
-
+            # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
+            opmodes = opcode.split("/") # split at "/"
+            v30b_op = opmodes.pop(0)    # first is the v3.0B
             # check instruction ends with dot
             rc_mode = v30b_op.endswith('.')
             if rc_mode:
@@ -188,9 +173,8 @@ class SVP64:
             if v30b_op not in svp64.instrs:
                 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
                                 (v30b_op, insn))
-            isa.instr[v30b_op].regs[0]
-            v30b_regs = isa.instr[v30b_op].regs[0]
-            rm = svp64.instrs[v30b_op]
+            v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
+            rm = svp64.instrs[v30b_op]             # one row of the svp64 RM CSV
             print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
             print ("v3.0B regs", opcode, v30b_regs)
             print (rm)
@@ -215,6 +199,8 @@ class SVP64:
                 rfield = rfield.split(";") # s:RA;d:CR1 etc.
                 for r in rfield:
                     rtype = r[0]
+                    # TODO: ignoring s/d makes it impossible to do
+                    # LD/ST-with-update.
                     r = r[2:] # ignore s: and d:
                     svp64_reg_byname[r] = i # this reg in EXTRA position 0-3
                     # check the regtype (if CR, record that)
@@ -471,6 +457,17 @@ class SVP64:
                 elif encmode == 'svm': # sub-vector mode
                     mapreduce_svm = True
 
+            # sanity-check that 2Pred mask is same mode
+            if has_pmask and has_smask:
+                assert smmode == pmmode, \
+                    "predicate masks %s and %s must be same reg type" % \
+                        (pme, sme)
+
+            # sanity-check that twin-predication mask only specified in 2P mode
+            if ptype == '1P':
+                assert has_smask == False, \
+                    "source-mask can only be specified on Twin-predicate ops"
+
             # construct the mode field, doing sanity-checking along the way
 
             if mapreduce_svm:
@@ -540,19 +537,10 @@ class SVP64:
                     assert rc_mode, "pr-mode BO only possible when Rc=1"
                     mode |= (predresult << 2) # set BO
 
-            # whewww.... modes all done... :)
+            # whewww.... modes all done :)
+            # now put into svp64_rm
             mode |= sv_mode
-
-            # sanity-check that 2Pred mask is same mode
-            if has_pmask and has_smask:
-                assert smmode == pmmode, \
-                    "predicate masks %s and %s must be same reg type" % \
-                        (pme, sme)
-
-            # sanity-check that twin-predication mask only specified in 2P mode
-            if ptype == '1P':
-                assert has_smask == False, \
-                    "source-mask can only be specified on Twin-predicate ops"
+            svp64_rm |= (mode << 19) # mode: bits 19-23
 
             # put in predicate masks into svp64_rm
             if ptype == '2P':
@@ -596,11 +584,11 @@ if __name__ == '__main__':
                  'sv.cmpi 5, 1, 3, 2',
                  'sv.setb 5, 31',
                  'sv.isel 64.v, 3, 2, 65.v',
-                 'sv.setb/m=r3.sm=1<<r3 5, 31',
+                 'sv.setb/m=r3/sm=1<<r3 5, 31',
                  'sv.setb/vec2 5, 31',
-                 'sv.setb/sw=8.ew=16 5, 31',
+                 'sv.setb/sw=8/ew=16 5, 31',
                  'sv.extsw./ff=eq 5, 31',
-                 'sv.extsw./satu.sz.dz.sm=r3.m=r3 5, 31',
+                 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
                  'sv.extsw./pr=eq 5.v, 31',
                 ])
     csvs = SVP64RM()