from collections import OrderedDict
from soc.decoder.pseudo.pagereader import ISA
-from soc.decoder.power_enums import get_csv, find_wiki_dir
+from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
-# identifies register by type
-def is_CR_3bit(regname):
- return regname in ['BF', 'BFA']
-
-def is_CR_5bit(regname):
- return regname in ['BA', 'BB', 'BC', 'BI', 'BT']
-
-def is_GPR(regname):
- return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
-
-def get_regtype(regname):
- if is_CR_3bit(regname):
- return "CR_3bit"
- if is_CR_5bit(regname):
- return "CR_5bit"
- if is_GPR(regname):
- return "GPR"
-
# decode GPR into sv extra
def get_extra_gpr(etype, regmode, field):
if regmode == 'scalar':
return sv_extra, field
-# gets SVP64 ReMap information
-class SVP64RM:
- def __init__(self):
- self.instrs = {}
- pth = find_wiki_dir()
- for fname in os.listdir(pth):
- if fname.startswith("RM"):
- for entry in get_csv(fname):
- self.instrs[entry['insn']] = entry
+# decodes SUBVL
+def decode_subvl(encoding):
+ pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
+ assert encoding in pmap, \
+ "encoding %s for SUBVL not recognised" % encoding
+ return pmap[encoding]
+
+
+# decodes elwidth
+def decode_elwidth(encoding):
+ pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
+ assert encoding in pmap, \
+ "encoding %s for elwidth not recognised" % encoding
+ return pmap[encoding]
+
+
+# decodes predicate register encoding
+def decode_predicate(encoding):
+ pmap = { # integer
+ '1<<r3': (0, 0b001),
+ 'r3' : (0, 0b010),
+ '~r3' : (0, 0b011),
+ 'r10' : (0, 0b100),
+ '~r10' : (0, 0b101),
+ 'r30' : (0, 0b110),
+ '~r30' : (0, 0b111),
+ # CR
+ 'lt' : (1, 0b000),
+ 'nl' : (1, 0b001), 'ge' : (1, 0b001), # same value
+ 'gt' : (1, 0b010),
+ 'ng' : (1, 0b011), 'le' : (1, 0b011), # same value
+ 'eq' : (1, 0b100),
+ 'ne' : (1, 0b101),
+ 'so' : (1, 0b110), 'un' : (1, 0b110), # same value
+ 'ns' : (1, 0b111), 'nu' : (1, 0b111), # same value
+ }
+ assert encoding in pmap, \
+ "encoding %s for predicate not recognised" % encoding
+ return pmap[encoding]
+
+
+# decodes "Mode" in similar way to BO field (supposed to, anyway)
+def decode_bo(encoding):
+ pmap = { # TODO: double-check that these are the same as Branch BO
+ 'lt' : 0b000,
+ 'nl' : 0b001, 'ge' : 0b001, # same value
+ 'gt' : 0b010,
+ 'ng' : 0b011, 'le' : 0b011, # same value
+ 'eq' : 0b100,
+ 'ne' : 0b101,
+ 'so' : 0b110, 'un' : 0b110, # same value
+ 'ns' : 0b111, 'nu' : 0b111, # same value
+ }
+ assert encoding in pmap, \
+ "encoding %s for BO Mode not recognised" % encoding
+ return pmap[encoding]
+
+# partial-decode fail-first mode
+def decode_ffirst(encoding):
+ if encoding in ['RC1', '~RC1']:
+ return encoding
+ return decode_bo(encoding)
# decodes svp64 assembly listings and creates EXT001 svp64 prefixes
# now find opcode fields
fields = ''.join(ls[1:]).split(',')
fields = list(map(str.strip, fields))
- print (opcode, fields)
+ print ("opcode, fields", ls, opcode, fields)
# identify if is a svp64 mnemonic
if not opcode.startswith('sv.'):
res.append(insn) # unaltered
continue
+ opcode = opcode[3:] # strip leading "sv."
+
+ # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
+ opmodes = opcode.split("/") # split at "/"
+ v30b_op = opmodes.pop(0) # first is the v3.0B
+ # check instruction ends with dot
+ rc_mode = v30b_op.endswith('.')
+ if rc_mode:
+ v30b_op = v30b_op[:-1]
- # start working on decoding the svp64 op: sv.baseop.vec2.mode
- opmodes = opcode.split(".")[1:] # strip leading "sv."
- v30b_op = opmodes.pop(0) # first is the v3.0B
if v30b_op not in isa.instr:
raise Exception("opcode %s of '%s' not supported" % \
(v30b_op, insn))
if v30b_op not in svp64.instrs:
raise Exception("opcode %s of '%s' not an svp64 instruction" % \
(v30b_op, insn))
- isa.instr[v30b_op].regs[0]
- v30b_regs = isa.instr[v30b_op].regs[0]
- rm = svp64.instrs[v30b_op]
+ v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
+ rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV
+ print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
print ("v3.0B regs", opcode, v30b_regs)
print (rm)
# first turn the svp64 rm into a "by name" dict, recording
# which position in the RM EXTRA it goes into
+ # also: record if the src or dest was a CR, for sanity-checking
+ # (elwidth overrides on CRs are banned)
+ decode = decode_extra(rm)
+ dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
svp64_reg_byname = {}
- for i in range(4):
- rfield = rm[str(i)]
- if not rfield or rfield == '0':
- continue
- print ("EXTRA field", i, rfield)
- rfield = rfield.split(";") # s:RA;d:CR1 etc.
- for r in rfield:
- r = r[2:] # ignore s: and d:
- svp64_reg_byname[r] = i # this reg in EXTRA position 0-3
+ svp64_reg_byname.update(svp64_src)
+ svp64_reg_byname.update(svp64_dest)
+
print ("EXTRA field index, by regname", svp64_reg_byname)
# okaaay now we identify the field value (opcode N,N,N) with
# the pseudo-code info (opcode RT, RA, RB)
+ assert len(fields) == len(v30b_regs), \
+ "length of fields %s must match insn `%s`" % \
+ (str(v30b_regs), insn)
opregfields = zip(fields, v30b_regs) # err that was easy
# now for each of those find its place in the EXTRA encoding
# great! got the extra fields in their associated positions:
# also we know the register type. now to create the EXTRA encodings
etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
+ ptype = rm['Ptype'] # Predication type: Twin / Single
extra_bits = 0
v30b_newfields = []
for extra_idx, (idx, field, regname, regtype) in extras.items():
print ("new v3.0B fields", v30b_op, v30b_newfields)
print ("extras", extras)
+
+ # rright. now we have all the info. start creating SVP64 RM
+ svp64_rm = 0b0
+
+ # begin with EXTRA fields
+ for idx, sv_extra in extras.items():
+ if idx is None: continue
+ # start at bit 10, work up 2/3 times EXTRA idx
+ offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
+ svp64_rm |= sv_extra << (10+idx*offs)
+
+ # parts of svp64_rm
+ mmode = 0 # bit 0
+ pmask = 0 # bits 1-3
+ destwid = 0 # bits 4-5
+ srcwid = 0 # bits 6-7
+ subvl = 0 # bits 8-9
+ smask = 0 # bits 16-18 but only for twin-predication
+ mode = 0 # bits 19-23
+
+ has_pmask = False
+ has_smask = False
+
+ saturation = None
+ src_zero = 0
+ dst_zero = 0
+ sv_mode = None
+
+ mapreduce = False
+ mapreduce_crm = False
+ mapreduce_svm = False
+
+ predresult = False
+ failfirst = False
+
+ # ok let's start identifying opcode augmentation fields
+ for encmode in opmodes:
+ # predicate mask (dest)
+ if encmode.startswith("m="):
+ pme = encmode
+ pmmode, pmask = decode_predicate(encmode[2:])
+ mmode = pmmode
+ has_pmask = True
+ # predicate mask (src, twin-pred)
+ elif encmode.startswith("sm="):
+ sme = encmode
+ smmode, smask = decode_predicate(encmode[3:])
+ mmode = smmode
+ has_smask = True
+ # vec2/3/4
+ elif encmode.startswith("vec"):
+ subvl = decode_subvl(encmode[3:])
+ # elwidth
+ elif encmode.startswith("ew="):
+ destwid = decode_elwidth(encmode[3:])
+ elif encmode.startswith("sw="):
+ srcwid = decode_elwidth(encmode[3:])
+ # saturation
+ elif encmode == 'sats':
+ assert sv_mode is None
+ saturation = 1
+ sv_mode = 0b10
+ elif encmode == 'satu':
+ assert sv_mode is None
+ sv_mode = 0b10
+ saturation = 0
+ # predicate zeroing
+ elif encmode == 'sz':
+ src_zero = 1
+ elif encmode == 'dz':
+ dst_zero = 1
+ # failfirst
+ elif encmode.startswith("ff="):
+ assert sv_mode is None
+ sv_mode = 0b01
+ failfirst = decode_ffirst(encmode[3:])
+ # predicate-result, interestingly same as fail-first
+ elif encmode.startswith("pr="):
+ assert sv_mode is None
+ sv_mode = 0b11
+ predresult = decode_ffirst(encmode[3:])
+ # map-reduce mode
+ elif encmode == 'mr':
+ assert sv_mode is None
+ sv_mode = 0b00
+ mapreduce = True
+ elif encmode == 'crm': # CR on map-reduce
+ assert sv_mode is None
+ sv_mode = 0b00
+ mapreduce_crm = True
+ elif encmode == 'svm': # sub-vector mode
+ mapreduce_svm = True
+
+ # sanity-check that 2Pred mask is same mode
+ if has_pmask and has_smask:
+ assert smmode == pmmode, \
+ "predicate masks %s and %s must be same reg type" % \
+ (pme, sme)
+
+ # sanity-check that twin-predication mask only specified in 2P mode
+ if ptype == '1P':
+ assert has_smask == False, \
+ "source-mask can only be specified on Twin-predicate ops"
+
+ # construct the mode field, doing sanity-checking along the way
+
+ if mapreduce_svm:
+ assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
+ assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
+
+ if src_zero:
+ assert has_smask, "src zeroing requires a source predicate"
+ if dst_zero:
+ assert has_pmask, "dest zeroing requires a dest predicate"
+
+ # "normal" mode
+ if sv_mode is None:
+ mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
+ sv_mode = 0b00
+
+ # "mapreduce" modes
+ elif sv_mode == 0b00:
+ mode |= (0b1<<2) # sets mapreduce
+ assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
+ if mapreduce_crm:
+ mode |= (0b1<<4) # sets CRM mode
+ assert rc_mode, "CRM only allowed when Rc=1"
+ # bit of weird encoding to jam zero-pred or SVM mode in.
+ # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
+ if subvl == 0:
+ mode |= (src_zero << 3) # predicate src-zeroing
+ elif mapreduce_svm:
+ mode |= (1 << 3) # SVM mode
+
+ # "failfirst" modes
+ elif sv_mode == 0b01:
+ assert dst_zero == 0, "dest-zero not allowed in failfirst mode"
+ if failfirst == 'RC1':
+ mode |= (0b1<<4) # sets RC1 mode
+ mode |= (src_zero << 3) # predicate src-zeroing
+ assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
+ elif failfirst == '~RC1':
+ mode |= (0b1<<4) # sets RC1 mode...
+ mode |= (src_zero << 3) # predicate src-zeroing
+ mode |= (0b1<<2) # ... with inversion
+ assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
+ else:
+ assert src_zero == 0, "src-zero not allowed in ffirst BO"
+ assert rc_mode, "ffirst BO only possible when Rc=1"
+ mode |= (failfirst << 2) # set BO
+
+ # "saturation" modes
+ elif sv_mode == 0b10:
+ mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
+ mode |= (saturation<<2) # sets signed/unsigned saturation
+
+ # "predicate-result" modes. err... code-duplication from ffirst
+ elif sv_mode == 0b11:
+ assert dst_zero == 0, "dest-zero not allowed in predresult mode"
+ if predresult == 'RC1':
+ mode |= (0b1<<4) # sets RC1 mode
+ mode |= (src_zero << 3) # predicate src-zeroing
+ assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
+ elif predresult == '~RC1':
+ mode |= (0b1<<4) # sets RC1 mode...
+ mode |= (src_zero << 3) # predicate src-zeroing
+ mode |= (0b1<<2) # ... with inversion
+ assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
+ else:
+ assert src_zero == 0, "src-zero not allowed in pr-mode BO"
+ assert rc_mode, "pr-mode BO only possible when Rc=1"
+ mode |= (predresult << 2) # set BO
+
+ # whewww.... modes all done :)
+ # now put into svp64_rm
+ mode |= sv_mode
+ svp64_rm |= (mode << 19) # mode: bits 19-23
+
+ # put in predicate masks into svp64_rm
+ if ptype == '2P':
+ svp64_rm |= (smask << 16) # source pred: bits 16-18
+ svp64_rm |= (mmode) # mask mode: bit 0
+ svp64_rm |= (pmask << 1) # 1-pred: bits 1-3
+
+ # and subvl
+ svp64_rm += (subvl << 8) # subvl: bits 8-9
+
+ # put in elwidths
+ svp64_rm += (srcwid << 6) # srcwid: bits 6-7
+ svp64_rm += (destwid << 4) # destwid: bits 4-5
+
+ # nice debug printout. (and now for something completely different)
+ # https://youtu.be/u0WOIwlXE9g?t=146
+ print ("svp64_rm", hex(svp64_rm), bin(svp64_rm))
+ print (" mmode 0 :", bin(mmode))
+ print (" pmask 1-3 :", bin(pmask))
+ print (" dstwid 4-5 :", bin(destwid))
+ print (" srcwid 6-7 :", bin(srcwid))
+ print (" subvl 8-9 :", bin(subvl))
+ print (" mode 19-23:", bin(mode))
+ offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
+ for idx, sv_extra in extras.items():
+ if idx is None: continue
+ start = (10+idx*offs)
+ end = start + offs-1
+ print (" extra%d %2d-%2d:" % (idx, start, end),
+ bin(sv_extra))
+ if ptype == '2P':
+ print (" smask 16-17:", bin(smask))
print ()
return res
'sv.extsw 5, 3',
'sv.cmpi 5, 1, 3, 2',
'sv.setb 5, 31',
- 'sv.isel 64.v, 3, 2, 65.v'
+ 'sv.isel 64.v, 3, 2, 65.v',
+ 'sv.setb/m=r3/sm=1<<r3 5, 31',
+ 'sv.setb/vec2 5, 31',
+ 'sv.setb/sw=8/ew=16 5, 31',
+ 'sv.extsw./ff=eq 5, 31',
+ 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
+ 'sv.extsw./pr=eq 5.v, 31',
])
csvs = SVP64RM()
projects / soc.git / blobdiff