from collections import OrderedDict
from soc.decoder.pseudo.pagereader import ISA
-from soc.decoder.power_enums import get_csv, find_wiki_dir
+from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
-# identifies register by type
-def is_CR_3bit(regname):
- return regname in ['BF', 'BFA']
-
-def is_CR_5bit(regname):
- return regname in ['BA', 'BB', 'BC', 'BI', 'BT']
-
-def is_GPR(regname):
- return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
-
-def get_regtype(regname):
- if is_CR_3bit(regname):
- return "CR_3bit"
- if is_CR_5bit(regname):
- return "CR_5bit"
- if is_GPR(regname):
- return "GPR"
-
# decode GPR into sv extra
def get_extra_gpr(etype, regmode, field):
if regmode == 'scalar':
return decode_bo(encoding)
-# gets SVP64 ReMap information
-class SVP64RM:
- def __init__(self):
- self.instrs = {}
- pth = find_wiki_dir()
- for fname in os.listdir(pth):
- if fname.startswith("RM"):
- for entry in get_csv(fname):
- self.instrs[entry['insn']] = entry
-
-
# decodes svp64 assembly listings and creates EXT001 svp64 prefixes
-class SVP64:
+class SVP64Asm:
def __init__(self, lst):
self.lst = lst
self.trans = self.translate(lst)
def __iter__(self):
- for insn in self.trans:
- yield insn
+ yield from self.trans
def translate(self, lst):
isa = ISA() # reads the v3.0B pseudo-code markdown files
svp64 = SVP64RM() # reads the svp64 Remap entries for registers
- res = []
for insn in lst:
# find first space, to get opcode
ls = insn.split(' ')
# identify if is a svp64 mnemonic
if not opcode.startswith('sv.'):
- res.append(insn) # unaltered
+ yield insn # unaltered
continue
opcode = opcode[3:] # strip leading "sv."
- # start working on decoding the svp64 op: sv.baseop/vec2.mode
- opcode = opcode.split("/") # split at "/"
- v30b_op = opcode[0] # first is the v3.0B
- if len(opcode) == 1:
- opmodes = [] # no sv modes
- else:
- opmodes = opcode[1].split(".") # second splits by dots
-
+ # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
+ opmodes = opcode.split("/") # split at "/"
+ v30b_op = opmodes.pop(0) # first is the v3.0B
# check instruction ends with dot
rc_mode = v30b_op.endswith('.')
if rc_mode:
if v30b_op not in svp64.instrs:
raise Exception("opcode %s of '%s' not an svp64 instruction" % \
(v30b_op, insn))
- isa.instr[v30b_op].regs[0]
- v30b_regs = isa.instr[v30b_op].regs[0]
- rm = svp64.instrs[v30b_op]
+ v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
+ rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV
print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
print ("v3.0B regs", opcode, v30b_regs)
print (rm)
# which position in the RM EXTRA it goes into
# also: record if the src or dest was a CR, for sanity-checking
# (elwidth overrides on CRs are banned)
- dest_reg_cr, src_reg_cr = False, False
+ decode = decode_extra(rm)
+ dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
svp64_reg_byname = {}
- for i in range(4):
- rfield = rm[str(i)]
- if not rfield or rfield == '0':
- continue
- print ("EXTRA field", i, rfield)
- rfield = rfield.split(";") # s:RA;d:CR1 etc.
- for r in rfield:
- rtype = r[0]
- r = r[2:] # ignore s: and d:
- svp64_reg_byname[r] = i # this reg in EXTRA position 0-3
- # check the regtype (if CR, record that)
- regtype = get_regtype(r)
- if regtype in ['CR_3bit', 'CR_5bit']:
- if rtype == 'd':
- dest_reg_cr = True
- if rtype == 'd':
- src_reg_cr = True
+ svp64_reg_byname.update(svp64_src)
+ svp64_reg_byname.update(svp64_dest)
print ("EXTRA field index, by regname", svp64_reg_byname)
# okaaay now we identify the field value (opcode N,N,N) with
# the pseudo-code info (opcode RT, RA, RB)
+ assert len(fields) == len(v30b_regs), \
+ "length of fields %s must match insn `%s`" % \
+ (str(v30b_regs), insn)
opregfields = zip(fields, v30b_regs) # err that was easy
# now for each of those find its place in the EXTRA encoding
elif encmode == 'svm': # sub-vector mode
mapreduce_svm = True
+ # sanity-check that 2Pred mask is same mode
+ if has_pmask and has_smask:
+ assert smmode == pmmode, \
+ "predicate masks %s and %s must be same reg type" % \
+ (pme, sme)
+
+ # sanity-check that twin-predication mask only specified in 2P mode
+ if ptype == '1P':
+ assert has_smask == False, \
+ "source-mask can only be specified on Twin-predicate ops"
+
# construct the mode field, doing sanity-checking along the way
if mapreduce_svm:
assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
+ if src_zero:
+ assert has_smask, "src zeroing requires a source predicate"
+ if dst_zero:
+ assert has_pmask, "dest zeroing requires a dest predicate"
+
# "normal" mode
if sv_mode is None:
- mode |= (src_zero << 3) | (dst_zero << 4)
+ mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
+ sv_mode = 0b00
# "mapreduce" modes
elif sv_mode == 0b00:
# "failfirst" modes
elif sv_mode == 0b01:
assert dst_zero == 0, "dest-zero not allowed in failfirst mode"
- mode |= 0b01 # sets failfirst
if failfirst == 'RC1':
mode |= (0b1<<4) # sets RC1 mode
mode |= (src_zero << 3) # predicate src-zeroing
assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
else:
assert src_zero == 0, "src-zero not allowed in ffirst BO"
+ assert rc_mode, "ffirst BO only possible when Rc=1"
mode |= (failfirst << 2) # set BO
- # sanity-check that 2Pred mask is same mode
- if has_pmask and has_smask:
- assert smmode == pmmode, \
- "predicate masks %s and %s must be same reg type" % \
- (pme, sme)
+ # "saturation" modes
+ elif sv_mode == 0b10:
+ mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
+ mode |= (saturation<<2) # sets signed/unsigned saturation
- # sanity-check that twin-predication mask only specified in 2P mode
- if ptype == '1P':
- assert has_smask == False, \
- "source-mask can only be specified on Twin-predicate ops"
+ # "predicate-result" modes. err... code-duplication from ffirst
+ elif sv_mode == 0b11:
+ assert dst_zero == 0, "dest-zero not allowed in predresult mode"
+ if predresult == 'RC1':
+ mode |= (0b1<<4) # sets RC1 mode
+ mode |= (src_zero << 3) # predicate src-zeroing
+ assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
+ elif predresult == '~RC1':
+ mode |= (0b1<<4) # sets RC1 mode...
+ mode |= (src_zero << 3) # predicate src-zeroing
+ mode |= (0b1<<2) # ... with inversion
+ assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
+ else:
+ assert src_zero == 0, "src-zero not allowed in pr-mode BO"
+ assert rc_mode, "pr-mode BO only possible when Rc=1"
+ mode |= (predresult << 2) # set BO
+
+ # whewww.... modes all done :)
+ # now put into svp64_rm
+ mode |= sv_mode
+ svp64_rm |= (mode << 19) # mode: bits 19-23
# put in predicate masks into svp64_rm
if ptype == '2P':
print (" smask 16-17:", bin(smask))
print ()
- return res
+ # first construct the prefix: EXT001, bits 7/9=1, in MSB0 order
+ svp64_prefix = 0x1 << (31-5) # EXT001
+ svp64_prefix |= 0x1 << (31-7) # SVP64 marker 1
+ svp64_prefix |= 0x1 << (31-9) # SVP64 marker 2
+ rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM
+ for i, x in enumerate(rmfields):
+ svp64_prefix |= ((svp64_rm>>i)&0b1) << (31-x)
+
+ # fiinally yield the svp64 prefix and the thingy. v3.0b opcode
+ yield ".long 0x%x" % svp64_prefix
+ yield "%s %s" % (v30b_op, ", ".join(v30b_newfields))
+ print ("new v3.0B fields", v30b_op, v30b_newfields)
if __name__ == '__main__':
- isa = SVP64(['slw 3, 1, 4',
+ isa = SVP64Asm(['slw 3, 1, 4',
'extsw 5, 3',
'sv.extsw 5, 3',
'sv.cmpi 5, 1, 3, 2',
'sv.setb 5, 31',
'sv.isel 64.v, 3, 2, 65.v',
- 'sv.setb/m=r3.sm=1<<r3 5, 31',
+ 'sv.setb/m=r3/sm=1<<r3 5, 31',
'sv.setb/vec2 5, 31',
- 'sv.setb/sw=8.ew=16 5, 31',
+ 'sv.setb/sw=8/ew=16 5, 31',
'sv.extsw./ff=eq 5, 31',
+ 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
+ 'sv.extsw./pr=eq 5.v, 31',
])
+ print ("list", list(isa))
csvs = SVP64RM()
projects / soc.git / blobdiff