Fix SVP64 translator to yield the unaltered instruction

[soc.git] / src / soc / sv / trans / svp64.py

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index 4c3b88af6d54c19ab9cef1d36addb320439c2ad9..a2427fd686004a926789ddf285496700c887fe6c 100644 (file)
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -118,13 +118,11 @@ class SVP64Asm:
         self.trans = self.translate(lst)
 
     def __iter__(self):
-        for insn in self.trans:
-            yield insn
+        yield from self.trans
 
     def translate(self, lst):
         isa = ISA() # reads the v3.0B pseudo-code markdown files
         svp64 = SVP64RM() # reads the svp64 Remap entries for registers
-        res = []
         for insn in lst:
             # find first space, to get opcode
             ls = insn.split(' ')
@@ -136,7 +134,7 @@ class SVP64Asm:
 
             # identify if is a svp64 mnemonic
             if not opcode.startswith('sv.'):
-                res.append(insn) # unaltered
+                yield insn  # unaltered
                 continue
             opcode = opcode[3:] # strip leading "sv."
 
@@ -540,7 +538,18 @@ class SVP64Asm:
                 print ("    smask  16-17:", bin(smask))
             print ()
 
-        return res
+            # first construct the prefix: EXT001, bits 7/9=1, in MSB0 order
+            svp64_prefix = 0x1 << (31-5) # EXT001
+            svp64_prefix |= 0x1 << (31-7) # SVP64 marker 1
+            svp64_prefix |= 0x1 << (31-9) # SVP64 marker 2
+            rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM
+            for i, x in enumerate(rmfields):
+                svp64_prefix |= ((svp64_rm>>i)&0b1) << (31-x)
+
+            # fiinally yield the svp64 prefix and the thingy.  v3.0b opcode
+            yield ".long 0x%x" % svp64_prefix
+            yield "%s %s" % (v30b_op, ", ".join(v30b_newfields))
+            print ("new v3.0B fields", v30b_op, v30b_newfields)
 
 if __name__ == '__main__':
     isa = SVP64Asm(['slw 3, 1, 4',