# decodes svp64 assembly listings and creates EXT001 svp64 prefixes
-class SVP64:
+class SVP64Asm:
def __init__(self, lst):
self.lst = lst
self.trans = self.translate(lst)
def __iter__(self):
- for insn in self.trans:
- yield insn
+ yield from self.trans
def translate(self, lst):
isa = ISA() # reads the v3.0B pseudo-code markdown files
svp64 = SVP64RM() # reads the svp64 Remap entries for registers
- res = []
for insn in lst:
# find first space, to get opcode
ls = insn.split(' ')
# identify if is a svp64 mnemonic
if not opcode.startswith('sv.'):
- res.append(insn) # unaltered
+ yield insn # unaltered
continue
opcode = opcode[3:] # strip leading "sv."
print (" smask 16-17:", bin(smask))
print ()
- return res
+ # first construct the prefix: EXT001, bits 7/9=1, in MSB0 order
+ svp64_prefix = 0x1 << (31-5) # EXT001
+ svp64_prefix |= 0x1 << (31-7) # SVP64 marker 1
+ svp64_prefix |= 0x1 << (31-9) # SVP64 marker 2
+ rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM
+ for i, x in enumerate(rmfields):
+ svp64_prefix |= ((svp64_rm>>i)&0b1) << (31-x)
+
+ # fiinally yield the svp64 prefix and the thingy. v3.0b opcode
+ yield ".long 0x%x" % svp64_prefix
+ yield "%s %s" % (v30b_op, ", ".join(v30b_newfields))
+ print ("new v3.0B fields", v30b_op, v30b_newfields)
if __name__ == '__main__':
- isa = SVP64(['slw 3, 1, 4',
+ isa = SVP64Asm(['slw 3, 1, 4',
'extsw 5, 3',
'sv.extsw 5, 3',
'sv.cmpi 5, 1, 3, 2',
'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
'sv.extsw./pr=eq 5.v, 31',
])
+ print ("list", list(isa))
csvs = SVP64RM()