X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fisa%2Fcaller.py;h=38a439f087d2827280c1ea9ac3669047448f2d20;hp=c1372a9a550117d37573970f7b7df7cd6dfda0ef;hb=5e3f4f16cdf9de7ebdaf5971f586475f5c623ca6;hpb=95f6cc49a70428354ce45962d21811b81f83b5fa

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index c1372a9a..38a439f0 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -242,14 +242,14 @@ class SVP64RMFields:
 
 
 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
-class SPP64PrefixFields:
+class SVP64PrefixFields:
     def __init__(self):
         self.insn = SelectableInt(0, 32)
         # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
         self.major = FieldSelectableInt(self.insn, tuple(range(0,6)))
         self.pid = FieldSelectableInt(self.insn, (7, 9)) # must be 0b11
         rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM
-        self.rm = FieldSelectableInt(self.spr, rmfields)
+        self.rm = FieldSelectableInt(self.insn, rmfields)
 
 
 class SPR(dict):
@@ -611,6 +611,10 @@ class ISACaller:
         # SVP64.  first, check if the opcode is EXT001
         yield Settle()
         opcode = yield self.dec2.dec.opcode_in
+        pfx = SVP64PrefixFields()
+        pfx.insn.value = opcode
+        major = pfx.major.asint(msb0=True) # MSB0 inversion
+        print ("prefix test: opcode:", major, bin(major))
 
     def execute_one(self):
         """execute one instruction