X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fisa%2Fcaller.py;h=4a38a1ede376a61c3402c20b46715dabfe4b92ce;hp=1dd24aeb9595db923cbade2dd23a2140401dcb76;hb=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71;hpb=a1fa36a7e48cca4b837752e72f93a069c6fa1747 diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 1dd24aeb..4a38a1ed 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -1,3 +1,7 @@ +# SPDX-License-Identifier: LGPLv3+ +# Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton +# Copyright (C) 2020 Michael Nolan +# Funded by NLnet http://nlnet.nl """core of the python-based POWER9 simulator this is part of a cycle-accurate POWER9 simulator. its primary purpose is @@ -9,15 +13,18 @@ related bugs: * https://bugs.libre-soc.org/show_bug.cgi?id=424 """ +from nmigen.back.pysim import Settle from functools import wraps from copy import copy from soc.decoder.orderedset import OrderedSet from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt, selectconcat) from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits, - insns, MicrOp) -from soc.decoder.helpers import exts + insns, MicrOp, In1Sel, In2Sel, In3Sel, + OutSel) +from soc.decoder.helpers import exts, gtu, ltu, undefined from soc.consts import PIb, MSRb # big-endian (PowerISA versions) +from soc.decoder.power_svp64 import SVP64RM, decode_extra from collections import namedtuple import math @@ -41,14 +48,31 @@ def swap_order(x, nbytes): return x +REG_SORT_ORDER = { + # TODO (lkcl): adjust other registers that should be in a particular order + # probably CA, CA32, and CR + "RT": 0, + "RA": 0, + "RB": 0, + "RS": 0, + "CR": 0, + "LR": 0, + "CTR": 0, + "TAR": 0, + "CA": 0, + "CA32": 0, + "MSR": 0, + + "overflow": 1, +} + + def create_args(reglist, extra=None): - args = OrderedSet() - for reg in reglist: - args.add(reg) - args = list(args) - if extra: - args = [extra] + args - return args + retval = list(OrderedSet(reglist)) + retval.sort(key=lambda reg: REG_SORT_ORDER[reg]) + if extra is not None: + return [extra] + retval + return retval class Mem: @@ -112,8 +136,8 @@ class Mem: staddr = addr remainder = addr & (self.bytes_per_word - 1) addr = addr >> self.word_log2 - print("Writing 0x{:x} to ST 0x{:x} memaddr 0x{:x}/{:x}".format(v, - staddr, addr, remainder, swap)) + print("Writing 0x{:x} to ST 0x{:x} " + "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap)) assert remainder & (width - 1) == 0, "Unaligned access unsupported!" if swap: v = swap_order(v, width) @@ -131,19 +155,21 @@ class Mem: print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr])) def __call__(self, addr, sz): - val = self.ld(addr.value, sz) + val = self.ld(addr.value, sz, swap=False) print("memread", addr, sz, val) return SelectableInt(val, sz*8) def memassign(self, addr, sz, val): print("memassign", addr, sz, val) - self.st(addr.value, val.value, sz) + self.st(addr.value, val.value, sz, swap=False) class GPR(dict): - def __init__(self, decoder, regfile): + def __init__(self, decoder, isacaller, svstate, regfile): dict.__init__(self) self.sd = decoder + self.isacaller = isacaller + self.svstate = svstate for i in range(32): self[i] = SelectableInt(regfile[i], 64) @@ -166,8 +192,11 @@ class GPR(dict): return rnum def ___getitem__(self, attr): - print("GPR getitem", attr) + """ XXX currently not used + """ rnum = self._get_regnum(attr) + offs = self.svstate.srcstep + print("GPR getitem", attr, rnum, "srcoffs", offs) return self.regfile[rnum] def dump(self): @@ -182,15 +211,59 @@ class GPR(dict): class PC: def __init__(self, pc_init=0): self.CIA = SelectableInt(pc_init, 64) - self.NIA = self.CIA + SelectableInt(4, 64) + self.NIA = self.CIA + SelectableInt(4, 64) # only true for v3.0B! + + def update_nia(self, is_svp64): + increment = 8 if is_svp64 else 4 + self.NIA = self.CIA + SelectableInt(increment, 64) - def update(self, namespace): + def update(self, namespace, is_svp64): + """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64 + """ self.CIA = namespace['NIA'].narrow(64) - self.NIA = self.CIA + SelectableInt(4, 64) + self.update_nia(is_svp64) namespace['CIA'] = self.CIA namespace['NIA'] = self.NIA +# Simple-V: see https://libre-soc.org/openpower/sv +class SVP64State: + def __init__(self, init=0): + self.spr = SelectableInt(init, 32) + # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/ + self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7))) + self.vl = FieldSelectableInt(self.spr, tuple(range(7,14))) + self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21))) + self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28))) + self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30))) + self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32))) + + +# SVP64 ReMap field +class SVP64RMFields: + def __init__(self, init=0): + self.spr = SelectableInt(init, 24) + # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/ + self.mmode = FieldSelectableInt(self.spr, [0]) + self.mask = FieldSelectableInt(self.spr, tuple(range(1,4))) + self.elwidth = FieldSelectableInt(self.spr, tuple(range(4,6))) + self.ewsrc = FieldSelectableInt(self.spr, tuple(range(6,8))) + self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10))) + self.extra = FieldSelectableInt(self.spr, tuple(range(10,19))) + self.mode = FieldSelectableInt(self.spr, tuple(range(19,24))) + + +# SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/ +class SVP64PrefixFields: + def __init__(self): + self.insn = SelectableInt(0, 32) + # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap + self.major = FieldSelectableInt(self.insn, tuple(range(0,6))) + self.pid = FieldSelectableInt(self.insn, (7, 9)) # must be 0b11 + rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM (ReMap) + self.rm = FieldSelectableInt(self.insn, rmfields) + + class SPR(dict): def __init__(self, dec2, initial_sprs={}): self.sd = dec2 @@ -216,6 +289,10 @@ class SPR(dict): if isinstance(key, int): key = spr_dict[key].SPR key = special_sprs.get(key, key) + if key == 'HSRR0': # HACK! + key = 'SRR0' + if key == 'HSRR1': # HACK! + key = 'SRR1' if key in self: res = dict.__getitem__(self, key) else: @@ -235,12 +312,78 @@ class SPR(dict): key = spr_dict[key].SPR print("spr key", key) key = special_sprs.get(key, key) + if key == 'HSRR0': # HACK! + self.__setitem__('SRR0', value) + if key == 'HSRR1': # HACK! + self.__setitem__('SRR1', value) print("setting spr", key, value) dict.__setitem__(self, key, value) def __call__(self, ridx): return self[ridx] +def get_pdecode_idx_in(dec2, name): + op = dec2.dec.op + in1_sel = yield op.in1_sel + in2_sel = yield op.in2_sel + in3_sel = yield op.in3_sel + # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec) + in1 = yield dec2.e.read_reg1.data + in2 = yield dec2.e.read_reg2.data + in3 = yield dec2.e.read_reg3.data + in1_isvec = yield dec2.in1_isvec + in2_isvec = yield dec2.in2_isvec + in3_isvec = yield dec2.in3_isvec + print ("get_pdecode_idx", in1_sel, In1Sel.RA.value, in1, in1_isvec) + # identify which regnames map to in1/2/3 + if name == 'RA': + if (in1_sel == In1Sel.RA.value or + (in1_sel == In1Sel.RA_OR_ZERO.value and in1 != 0)): + return in1, in1_isvec + if in1_sel == In1Sel.RA_OR_ZERO.value: + return in1, in1_isvec + elif name == 'RB': + if in2_sel == In2Sel.RB.value: + return in2, in2_isvec + if in3_sel == In3Sel.RB.value: + return in3, in3_isvec + # XXX TODO, RC doesn't exist yet! + elif name == 'RC': + assert False, "RC does not exist yet" + elif name == 'RS': + if in1_sel == In1Sel.RS.value: + return in1, in1_isvec + if in2_sel == In2Sel.RS.value: + return in2, in2_isvec + if in3_sel == In3Sel.RS.value: + return in3, in3_isvec + return None, False + + +def get_pdecode_idx_out(dec2, name): + op = dec2.dec.op + out_sel = yield op.out_sel + # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec) + out = yield dec2.e.write_reg.data + o_isvec = yield dec2.o_isvec + print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec) + # identify which regnames map to out / o2 + if name == 'RA': + if out_sel == OutSel.RA.value: + return out, o_isvec + elif name == 'RT': + if out_sel == OutSel.RT.value: + return out, o_isvec + print ("get_pdecode_idx_out not found", name) + return None, False + + +# XXX TODO +def get_pdecode_idx_out2(dec2, name): + op = dec2.dec.op + print ("TODO: get_pdecode_idx_out2", name) + return None, False + class ISACaller: # decoder2 - an instance of power_decoder2 @@ -249,6 +392,7 @@ class ISACaller: # respect_pc - tracks the program counter. requires initial_insns def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0, initial_mem=None, initial_msr=0, + initial_svstate=0, initial_insns=None, respect_pc=False, disassembly=None, initial_pc=0, @@ -256,6 +400,7 @@ class ISACaller: self.bigendian = bigendian self.halted = False + self.is_svp64_mode = False self.respect_pc = respect_pc if initial_sprs is None: initial_sprs = {} @@ -285,7 +430,11 @@ class ISACaller: self.disassembly[i*4 + disasm_start] = code # set up registers, instruction memory, data memory, PC, SPRs, MSR - self.gpr = GPR(decoder2, regfile) + self.svp64rm = SVP64RM() + if isinstance(initial_svstate, int): + initial_svstate = SVP64State(initial_svstate) + self.svstate = initial_svstate + self.gpr = GPR(decoder2, self, self.svstate, regfile) self.mem = Mem(row_bytes=8, initial_mem=initial_mem) self.imem = Mem(row_bytes=4, initial_mem=initial_insns) self.pc = PC() @@ -306,11 +455,12 @@ class ISACaller: # 3.2.3 p46 p232 VRSAVE (actually SPR #256) # create CR then allow portions of it to be "selectable" (below) - self._cr = SelectableInt(initial_cr, 64) # underlying reg - self.cr = FieldSelectableInt(self._cr, list(range(32, 64))) + #rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2) + self.cr = SelectableInt(initial_cr, 64) # underlying reg + #self.cr = FieldSelectableInt(self._cr, list(range(32, 64))) # "undefined", just set to variable-bit-width int (use exts "max") - self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256! + #self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256! self.namespace = {} self.namespace.update(self.spr) @@ -322,7 +472,7 @@ class ISACaller: 'CIA': self.pc.CIA, 'CR': self.cr, 'MSR': self.msr, - 'undefined': self.undefined, + 'undefined': undefined, 'mode_is_64bit': True, 'SO': XER_bits['SO'] }) @@ -333,7 +483,7 @@ class ISACaller: # field-selectable versions of Condition Register TODO check bitranges? self.crl = [] for i in range(8): - bits = tuple(range(i*4, (i+1)*4)) # errr... maybe? + bits = tuple(range(i*4+32, (i+1)*4+32)) # errr... maybe? _cr = FieldSelectableInt(self.cr, bits) self.crl.append(_cr) self.namespace["CR%d" % i] = _cr @@ -388,7 +538,10 @@ class ISACaller: else: sig = getattr(fields, name) val = yield sig - if name in ['BF', 'BFA']: + # these are all opcode fields involved in index-selection of CR, + # and need to do "standard" arithmetic. CR[BA+32] for example + # would, if using SelectableInt, only be 5-bit. + if name in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']: self.namespace[name] = val else: self.namespace[name] = SelectableInt(val, sig.width) @@ -398,7 +551,7 @@ class ISACaller: self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value def handle_carry_(self, inputs, outputs, already_done): - inv_a = yield self.dec2.e.do.invert_a + inv_a = yield self.dec2.e.do.invert_in if inv_a: inputs[0] = ~inputs[0] @@ -415,28 +568,45 @@ class ISACaller: gts = [] for x in inputs: print("gt input", x, output) - gt = (x > output) + gt = (gtu(x, output)) gts.append(gt) print(gts) cy = 1 if any(gts) else 0 + print("CA", cy, gts) if not (1 & already_done): self.spr['XER'][XER_bits['CA']] = cy - print("inputs", inputs) + print("inputs", already_done, inputs) # 32 bit carry - gts = [] - for x in inputs: - print("input", x, output) - gt = (x[32:64] > output[32:64]) == SelectableInt(1, 1) - gts.append(gt) - cy32 = 1 if any(gts) else 0 + # ARGH... different for OP_ADD... *sigh*... + op = yield self.dec2.e.do.insn_type + if op == MicrOp.OP_ADD.value: + res32 = (output.value & (1 << 32)) != 0 + a32 = (inputs[0].value & (1 << 32)) != 0 + if len(inputs) >= 2: + b32 = (inputs[1].value & (1 << 32)) != 0 + else: + b32 = False + cy32 = res32 ^ a32 ^ b32 + print("CA32 ADD", cy32) + else: + gts = [] + for x in inputs: + print("input", x, output) + print(" x[32:64]", x, x[32:64]) + print(" o[32:64]", output, output[32:64]) + gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1) + gts.append(gt) + cy32 = 1 if any(gts) else 0 + print("CA32", cy32, gts) if not (2 & already_done): self.spr['XER'][XER_bits['CA32']] = cy32 def handle_overflow(self, inputs, outputs, div_overflow): - inv_a = yield self.dec2.e.do.invert_a - if inv_a: - inputs[0] = ~inputs[0] + if hasattr(self.dec2.e.do, "invert_in"): + inv_a = yield self.dec2.e.do.invert_in + if inv_a: + inputs[0] = ~inputs[0] imm_ok = yield self.dec2.e.do.imm_data.ok if imm_ok: @@ -475,6 +645,8 @@ class ISACaller: def handle_comparison(self, outputs): out = outputs[0] + assert isinstance(out, SelectableInt), \ + "out zero not a SelectableInt %s" % repr(outputs) print("handle_comparison", out.bits, hex(out.value)) # TODO - XXX *processor* in 32-bit mode # https://bugs.libre-soc.org/show_bug.cgi?id=424 @@ -493,7 +665,7 @@ class ISACaller: def set_pc(self, pc_val): self.namespace['NIA'] = SelectableInt(pc_val, 64) - self.pc.update(self.namespace) + self.pc.update(self.namespace, self.is_svp64_mode) def setup_one(self): """set up one instruction @@ -509,49 +681,94 @@ class ISACaller: print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins))) print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value) + yield self.dec2.sv_rm.eq(0) yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) yield self.dec2.dec.bigendian.eq(self.bigendian) - yield self.dec2.msr.eq(self.msr.value) - yield self.dec2.cia.eq(pc) + yield self.dec2.state.msr.eq(self.msr.value) + yield self.dec2.state.pc.eq(pc) + + # SVP64. first, check if the opcode is EXT001, and SVP64 id bits set + yield Settle() + opcode = yield self.dec2.dec.opcode_in + pfx = SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder + pfx.insn.value = opcode + major = pfx.major.asint(msb0=True) # MSB0 inversion + print ("prefix test: opcode:", major, bin(major), + pfx.insn[7] == 0b1, pfx.insn[9] == 0b1) + self.is_svp64_mode = ((major == 0b000001) and + pfx.insn[7].value == 0b1 and + pfx.insn[9].value == 0b1) + self.pc.update_nia(self.is_svp64_mode) + if not self.is_svp64_mode: + return + + # in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction + print ("svp64.rm", bin(pfx.rm.asint(msb0=True))) + print (" svstate.vl", self.svstate.vl.asint(msb0=True)) + print (" svstate.mvl", self.svstate.maxvl.asint(msb0=True)) + sv_rm = pfx.rm.asint() + ins = self.imem.ld(pc+4, 4, False, True) + print(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins))) + yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix + yield self.dec2.sv_rm.eq(sv_rm) # svp64 prefix + yield Settle() def execute_one(self): """execute one instruction """ # get the disassembly code for this instruction - code = self.disassembly[self._pc] - print("sim-execute", hex(self._pc), code) + if self.is_svp64_mode: + code = self.disassembly[self._pc+4] + print(" svp64 sim-execute", hex(self._pc), code) + else: + code = self.disassembly[self._pc] + print("sim-execute", hex(self._pc), code) opname = code.split(' ')[0] yield from self.call(opname) + # don't use this except in special circumstances if not self.respect_pc: self.fake_pc += 4 + print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value) def get_assembly_name(self): # TODO, asmregs is from the spec, e.g. add RT,RA,RB # see http://bugs.libre-riscv.org/show_bug.cgi?id=282 + dec_insn = yield self.dec2.e.do.insn asmcode = yield self.dec2.dec.op.asmcode - print("get assembly name asmcode", asmcode) + print("get assembly name asmcode", asmcode, hex(dec_insn)) asmop = insns.get(asmcode, None) int_op = yield self.dec2.dec.op.internal_op # sigh reconstruct the assembly instruction name - ov_en = yield self.dec2.e.do.oe.oe - ov_ok = yield self.dec2.e.do.oe.ok - rc_en = yield self.dec2.e.do.rc.data - rc_ok = yield self.dec2.e.do.rc.ok + if hasattr(self.dec2.e.do, "oe"): + ov_en = yield self.dec2.e.do.oe.oe + ov_ok = yield self.dec2.e.do.oe.ok + else: + ov_en = False + ov_ok = False + if hasattr(self.dec2.e.do, "rc"): + rc_en = yield self.dec2.e.do.rc.rc + rc_ok = yield self.dec2.e.do.rc.ok + else: + rc_en = False + rc_ok = False # grrrr have to special-case MUL op (see DecodeOE) - print("ov en rc en", ov_ok, ov_en, rc_ok, rc_en, int_op) + print("ov %d en %d rc %d en %d op %d" % + (ov_ok, ov_en, rc_ok, rc_en, int_op)) if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]: print("mul op") if rc_en & rc_ok: asmop += "." else: - if ov_en & ov_ok: - asmop += "." - lk = yield self.dec2.e.do.lk - if lk: - asmop += "l" + if not asmop.endswith("."): # don't add "." to "andis." + if rc_en & rc_ok: + asmop += "." + if hasattr(self.dec2.e.do, "lk"): + lk = yield self.dec2.e.do.lk + if lk: + asmop += "l" print("int_op", int_op) if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]: AA = yield self.dec2.dec.fields.FormI.AA[0:-1] @@ -578,6 +795,8 @@ class ISACaller: return dec_insn & (1 << 20) != 0 # sigh - XFF.spr[-1]? def call(self, name): + """call(opcode) - the primary execution point for instructions + """ name = name.strip() # remove spaces if not already done so if self.halted: print("halted - not executing", name) @@ -610,7 +829,7 @@ class ISACaller: if instr_is_privileged and self.msr[MSRb.PR] == 1: self.TRAP(0x700, PIb.PRIV) self.namespace['NIA'] = self.trap_nia - self.pc.update(self.namespace) + self.pc.update(self.namespace, self.is_svp64_mode) return # check halted condition @@ -624,9 +843,10 @@ class ISACaller: illegal = name != asmop if illegal: + print("illegal", name, asmop) self.TRAP(0x700, PIb.ILLEG) self.namespace['NIA'] = self.trap_nia - self.pc.update(self.namespace) + self.pc.update(self.namespace, self.is_svp64_mode) print("name %s != %s - calling ILLEGAL trap, PC: %x" % (name, asmop, self.pc.CIA.value)) return @@ -639,14 +859,37 @@ class ISACaller: list(info.uninit_regs)) print(input_names) - # main registers (RT, RA ...) + # get SVP64 entry for the current instruction + sv_rm = self.svp64rm.instrs.get(name) + if sv_rm is not None: + dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm) + else: + dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {} + print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname) + + # get SVSTATE srcstep. TODO: dststep (twin predication) + srcstep = self.svstate.srcstep.asint(msb0=True) + + # main input registers (RT, RA ...) inputs = [] for name in input_names: - regnum = yield getattr(self.decoder, name) + # using PowerDecoder2, first, find the decoder index. + # (mapping name RA RB RC RS to in1, in2, in3) + regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name) + if regnum is None: + # doing this is not part of svp64, it's because output + # registers, to be modified, need to be in the namespace. + regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name) + # here's where we go "vector". TODO: zero-testing (RA_IS_ZERO) + if is_vec: + regnum += srcstep # TODO, elwidth overrides + + # in case getting the register number is needed, _RA, _RB regname = "_" + name self.namespace[regname] = regnum - print('reading reg %d' % regnum) - inputs.append(self.gpr(regnum)) + print('reading reg %s %d' % (name, regnum), is_vec) + reg_val = self.gpr(regnum) + inputs.append(reg_val) # "special" registers for special in info.special_regs: @@ -680,7 +923,10 @@ class ISACaller: already_done |= 2 print("carry already done?", bin(already_done)) - carry_en = yield self.dec2.e.do.output_carry + if hasattr(self.dec2.e.do, "output_carry"): + carry_en = yield self.dec2.e.do.output_carry + else: + carry_en = False if carry_en: yield from self.handle_carry_(inputs, results, already_done) @@ -691,16 +937,26 @@ class ISACaller: if name == 'overflow': overflow = output - ov_en = yield self.dec2.e.do.oe.oe - ov_ok = yield self.dec2.e.do.oe.ok + if hasattr(self.dec2.e.do, "oe"): + ov_en = yield self.dec2.e.do.oe.oe + ov_ok = yield self.dec2.e.do.oe.ok + else: + ov_en = False + ov_ok = False print("internal overflow", overflow, ov_en, ov_ok) if ov_en & ov_ok: yield from self.handle_overflow(inputs, results, overflow) - rc_en = yield self.dec2.e.do.rc.data + if hasattr(self.dec2.e.do, "rc"): + rc_en = yield self.dec2.e.do.rc.rc + else: + rc_en = False if rc_en: self.handle_comparison(results) + # svp64 loop can end early if the dest is scalar + svp64_dest_vector = False + # any modified return results? if info.write_regs: for name, output in zip(output_names, results): @@ -723,15 +979,48 @@ class ISACaller: if name == 'MSR': print('msr written', hex(self.msr.value)) else: - regnum = yield getattr(self.decoder, name) - print('writing reg %d %s' % (regnum, str(output))) + regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, + name) + if regnum is None: + # temporary hack for not having 2nd output + regnum = yield getattr(self.decoder, name) + is_vec = False + # here's where we go "vector". + if is_vec: + regnum += srcstep # TODO, elwidth overrides + svp64_dest_vector = True + print('writing reg %d %s' % (regnum, str(output)), is_vec) if output.bits > 64: output = SelectableInt(output.value, 64) self.gpr[regnum] = output - print("end of call", self.namespace['CIA'], self.namespace['NIA']) + # check if it is the SVSTATE.src/dest step that needs incrementing + # this is our Sub-Program-Counter loop from 0 to VL-1 + if self.is_svp64_mode: + # XXX twin predication TODO + vl = self.svstate.vl.asint(msb0=True) + mvl = self.svstate.maxvl.asint(msb0=True) + srcstep = self.svstate.srcstep.asint(msb0=True) + print (" svstate.vl", vl) + print (" svstate.mvl", mvl) + print (" svstate.srcstep", srcstep) + # check if srcstep needs incrementing by one, stop PC advancing + if svp64_dest_vector and srcstep != vl-1: + self.svstate.srcstep += SelectableInt(1, 7) + self.pc.NIA.value = self.pc.CIA.value + self.namespace['NIA'] = self.pc.NIA + print("end of sub-pc call", self.namespace['CIA'], + self.namespace['NIA']) + return # DO NOT allow PC to update whilst Sub-PC loop running + # reset to zero + self.svstate.srcstep[0:7] = 0 + print (" svstate.srcstep loop end (PC to update)") + self.pc.update_nia(self.is_svp64_mode) + self.namespace['NIA'] = self.pc.NIA + # UPDATE program counter - self.pc.update(self.namespace) + self.pc.update(self.namespace, self.is_svp64_mode) + print("end of call", self.namespace['CIA'], self.namespace['NIA']) def inject():