X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fisa%2Ftest_caller.py;h=691d9a71357b2fd2211e946fa0f4d731f2b70775;hp=684b38aae51f022dcb8e0cae615d9fee318fc332;hb=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71;hpb=5d91d698a990e8bb6c32896adac3ae8f59de027f diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 684b38aa..691d9a71 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -16,7 +16,9 @@ class Register: def __init__(self, num): self.num = num -def run_tst(generator, initial_regs, initial_sprs={}): +def run_tst(generator, initial_regs, initial_sprs=None, svstate=0): + if initial_sprs is None: + initial_sprs = {} m = Module() comb = m.d.comb instruction = Signal(32) @@ -30,6 +32,7 @@ def run_tst(generator, initial_regs, initial_sprs={}): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) simulator = ISA(pdecode2, initial_regs, initial_sprs, 0, initial_insns=gen, respect_pc=True, + initial_svstate=svstate, disassembly=insncode, bigendian=0) comb += pdecode2.dec.raw_opcode_in.eq(instruction) @@ -38,6 +41,7 @@ def run_tst(generator, initial_regs, initial_sprs={}): def process(): + yield pdecode2.dec.bigendian.eq(0) # little / big? pc = simulator.pc.CIA.value index = pc//4 while index < len(instructions): @@ -49,15 +53,12 @@ def run_tst(generator, initial_regs, initial_sprs={}): yield Settle() ins, code = instructions[index] - print("0x{:X}".format(ins & 0xffffffff)) - print(code) + print(" 0x{:X}".format(ins & 0xffffffff)) + opname = code.split(' ')[0] + print(code, opname) # ask the decoder to decode this binary data (endian'd) - yield pdecode2.dec.bigendian.eq(0) # little / big? - yield instruction.eq(ins) # raw binary instr. - yield Delay(1e-6) - opname = code.split(' ')[0] - yield from simulator.call(opname) + yield from simulator.execute_one() pc = simulator.pc.CIA.value index = pc//4