X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=blobdiff_plain;f=src%2Fsoc%2Fdecoder%2Fpower_pseudo.py;h=3e02cb78a37c313d42800a58eb410d57655d63b0;hp=f2e575e8c5b707e7ec2f8d2ea6ca6d36060e08ad;hb=5963eef6679f6833b6b8f854868d90480e3753b2;hpb=af3c6727c8bb59623bf5672b867407b5516e8338

diff --git a/src/soc/decoder/power_pseudo.py b/src/soc/decoder/power_pseudo.py
index f2e575e8..3e02cb78 100644
--- a/src/soc/decoder/power_pseudo.py
+++ b/src/soc/decoder/power_pseudo.py
@@ -21,6 +21,8 @@ from nmigen import Module, Signal
 
 from soc.decoder.pseudo.parser import GardenSnakeCompiler
 from soc.decoder.selectable_int import SelectableInt, selectconcat
+from soc.decoder.isa.caller import GPR, Mem
+
 
 ####### Test code #######
 
@@ -96,17 +98,112 @@ addpcis = """
 D <- d0||d1||d2
 """
 
+testmul = """
+x <- [0] * 16
+RT <- (RA) + EXTS(SI || [0]*16)
+"""
+
+testgetzero = """
+RS <- (RA|0)
+RS <- RS + 1
+print(RS)
+"""
+
+testcat = """
+RT <- (load_data[56:63] || load_data[48:55]
+    || load_data[40:47] || load_data[32:39]
+    || load_data[24:31] || load_data[16:23]
+    || load_data[8:15]  || load_data[0:7])
+"""
+
+testgpr = """
+GPR(5) <- x
+"""
+testmem = """
+a <- (RA|0)
+b <- (RB|0)
+RA <- MEM(RB, 2)
+EA <- a + 1
+MEM(EA, 1) <- (RS)[56:63]
+RB <- RA
+RA <- EA
+"""
+
+testgprslice = """
+MEM(EA, 4) <- GPR(r)[32:63]
+#x <- x[0][32:63]
+"""
+
+testdo = r"""
+do i = 0 to 7
+    print(i)
+"""
+
+testcond = """
+ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
+cond_ok <- BO[0] | ¬(CR[BI+32] ^  BO[1])
+"""
+
+lswx = """
+if RA = 0 then EA <- 0
+else           EA <- (RA)
+if NB = 0 then n <-  32
+else           n <-  NB
+r <- RT - 1
+i <- 32
+do while n > 0
+    if i = 32 then
+        r <- (r + 1) % 32
+        GPR(r) <- 0
+    GPR(r)[i:i+7] <- MEM(EA, 1)
+    i <- i + 8
+    if i = 64 then i <- 32
+    EA <- EA + 1
+    n <- n - 1
+"""
+
+_lswx = """
+GPR(r)[x] <- 1
+"""
+
+switchtest = """
+switch (n)
+    case(1): x <- 5
+    case(2): fallthrough
+    case(3):
+        x <- 3
+    case(4): fallthrough
+    default:
+        x <- 9
+"""
+
+hextest = """
+RT <- 0x0001_a000_0000_0000
+"""
+
+code = hextest
+#code = lswx
+#code = testcond
+#code = testdo
+#code = _bpermd
+#code = testmul
+#code = testgetzero
+#code = testcat
+#code = testgpr
+#code = testmem
+#code = testgprslice
 #code = testreg
-code = cnttzd
+#code = cnttzd
 #code = cmpi
 #code = cmpeqb
 #code = addpcis
 #code = bpermd
 
+
 def tolist(num):
     l = []
     for i in range(64):
-        l.append(1 if (num & (1<<i)) else 0)
+        l.append(1 if (num & (1 << i)) else 0)
     l.reverse()
     return l
 
@@ -115,89 +212,72 @@ def get_reg_hex(reg):
     return hex(reg.value)
 
 
-class GPR(dict):
-    def __init__(self, sd, regfile):
-        dict.__init__(self)
-        self.sd = sd
-        self.regfile = regfile
-        for i in range(32):
-            self[i] = SelectableInt(0, 64)
-
-    def set_form(self, form):
-        self.form = form
-
-    def ___getitem__(self, attr):
-        print ("GPR getitem", attr)
-        getform = self.sd.sigforms[self.form]
-        rnum = getattr(getform, attr)
-        print ("GPR get", rnum, rnum, dir(rnum))
-        l = list(rnum)
-        print (l[0]._as_const())
-        #for x in rnum:
-            #print (x, x.value, dir(x))
-            #print (x.value, dir(x.value))
-        print (list(rnum))
-        return self.regfile[rnum]
+def convert_to_python(pcode, form, incl_carry):
 
-
-def convert_to_python(pcode):
-
-    gsc = GardenSnakeCompiler()
+    print("form", form)
+    gsc = GardenSnakeCompiler(form=form, incl_carry=incl_carry)
 
     tree = gsc.compile(pcode, mode="exec", filename="string")
     tree = ast.fix_missing_locations(tree)
     regsused = {'read_regs': gsc.parser.read_regs,
                 'write_regs': gsc.parser.write_regs,
-                'uninit_regs': gsc.parser.uninit_regs}
+                'uninit_regs': gsc.parser.uninit_regs,
+                'special_regs': gsc.parser.special_regs,
+                'op_fields': gsc.parser.op_fields}
     return astor.to_source(tree), regsused
 
 
 def test():
 
-    gsc = GardenSnakeCompiler()
+    gsc = GardenSnakeCompiler(debug=True)
 
-    # XXX unused!  see GPR instead
     gsc.regfile = {}
     for i in range(32):
-        gsc.regfile[i] = 0
+        gsc.regfile[i] = i
     gsc.gpr = GPR(gsc.parser.sd, gsc.regfile)
+    gsc.mem = Mem()
 
     _compile = gsc.compile
 
     tree = _compile(code, mode="single", filename="string")
     tree = ast.fix_missing_locations(tree)
-    print ( ast.dump(tree) )
+    print(ast.dump(tree))
 
-    print ("astor dump")
-    print (astor.dump_tree(tree))
-    print ("to source")
+    print("astor dump")
+    print(astor.dump_tree(tree))
+    print("to source")
     source = astor.to_source(tree)
-    print (source)
+    print(source)
 
-    #sys.exit(0)
+    # sys.exit(0)
 
     # Set up the GardenSnake run-time environment
     def print_(*args):
-        print ("args", args)
-        print ("-->", " ".join(map(str,args)))
+        print("args", args)
+        print("-->", " ".join(map(str, args)))
 
-    from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,)
+    from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,
+                                     trunc_div, trunc_rem)
 
     d = {}
     d["print"] = print_
     d["EXTS64"] = EXTS64
     d["EXTZ64"] = EXTZ64
+    d["trunc_div"] = trunc_div
+    d["trunc_rem"] = trunc_rem
     d["SelectableInt"] = SelectableInt
     d["concat"] = selectconcat
     d["GPR"] = gsc.gpr
+    d["MEM"] = gsc.mem
+    d["memassign"] = gsc.mem.memassign
 
     form = 'X'
     gsc.gpr.set_form(form)
     getform = gsc.parser.sd.sigforms[form]._asdict()
     #print ("getform", form)
-    #for k, f in getform.items():
-        #print (k, f)
-        #d[k] = getform[k]
+    # for k, f in getform.items():
+    #print (k, f)
+    #d[k] = getform[k]
 
     compiled_code = compile(source, mode="exec", filename="<string>")
 
@@ -205,7 +285,7 @@ def test():
     comb = m.d.comb
     instruction = Signal(32)
 
-    m.submodules.decode = decode =  gsc.parser.sd
+    m.submodules.decode = decode = gsc.parser.sd
     comb += decode.raw_opcode_in.eq(instruction)
     sim = Simulator(m)
 
@@ -222,30 +302,33 @@ def test():
 
             # uninitialised regs, drop them into dict for function
             for rname in gsc.parser.uninit_regs:
-                d[rname] = SelectableInt(0, 64) # uninitialised (to zero)
-                print ("uninitialised", rname, get_reg_hex(d[rname]))
+                d[rname] = SelectableInt(0, 64)  # uninitialised (to zero)
+                print("uninitialised", rname, hex(d[rname].value))
 
             # read regs, drop them into dict for function
             for rname in gsc.parser.read_regs:
                 regidx = yield getattr(decode.sigforms['X'], rname)
-                d[rname] = gsc.gpr[regidx]
-                print ("read reg", rname, regidx, get_reg_hex(d[rname]))
+                d[rname] = gsc.gpr[regidx]  # contents of regfile
+                d["_%s" % rname] = regidx  # actual register value
+                print("read reg", rname, regidx, hex(d[rname].value))
 
-            exec (compiled_code, d) # code gets executed here in dict "d"
-            print ("Done")
+            exec(compiled_code, d)  # code gets executed here in dict "d"
+            print("Done")
 
-            print (d.keys()) # shows the variables that may have been created
+            print(d.keys())  # shows the variables that may have been created
 
-            print (decode.sigforms['X'])
+            print(decode.sigforms['X'])
             x = yield decode.sigforms['X'].RS
             ra = yield decode.sigforms['X'].RA
-            print ("RA", ra, d['RA'])
-            print ("RS", x)
+            rb = yield decode.sigforms['X'].RB
+            print("RA", ra, d['RA'])
+            print("RB", rb, d['RB'])
+            print("RS", x)
 
             for wname in gsc.parser.write_regs:
                 reg = getform[wname]
-                print ("write regs", wname, d[wname], reg)
                 regidx = yield reg
+                print("write regs", regidx, wname, d[wname], reg)
                 gsc.gpr[regidx] = d[wname]
 
     sim.add_process(process)
@@ -253,8 +336,14 @@ def test():
                        traces=decode.ports()):
         sim.run()
 
-    for i in range(len(gsc.gpr)):
-        print ("regfile", i, get_reg_hex(gsc.gpr[i]))
+    gsc.gpr.dump()
+
+    for i in range(0, len(gsc.mem.mem), 16):
+        hexstr = []
+        for j in range(16):
+            hexstr.append("%02x" % gsc.mem.mem[i+j])
+        hexstr = ' '.join(hexstr)
+        print("mem %4x" % i, hexstr)
 
 
 if __name__ == '__main__':