X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=blobdiff_plain;f=src%2Fsoc%2Fexperiment%2Ficache.py;h=fb01baf4f1d811c628c688fff0685f7122dae8fe;hp=06031af0268862ac5f862d281a1945bf833e7013;hb=41d2c31f6f0d184a57f468d5b157d6e8c0a44af1;hpb=26e84dc5d35f80bd4a25e05ea94f7f3e3bd7a4c6

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 06031af0..fb01baf4 100644
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -45,10 +45,10 @@ from nmigen_soc.wishbone.sram import SRAM
 from nmigen import Memory
 from nmutil.util import wrap
 from nmigen.cli import main, rtlil
-if True:
-    from nmigen.back.pysim import Simulator, Delay, Settle
-else:
-    from nmigen.sim.cxxsim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
 
 
 SIM            = 0