X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=blobdiff_plain;f=src%2Fsoc%2Fexperiment%2Ftest%2Ftest_mmu_dcache.py;h=1528d7d40db31bbaed8f821a7a90663ef087bb26;hp=1fd58c073c35831563a5efe97655d83fa52c21f3;hb=9885585d097ca1f26283fa9dc0f22a4fa7bc026c;hpb=ce342366a596119b4321af5919ef26979653b453

diff --git a/src/soc/experiment/test/test_mmu_dcache.py b/src/soc/experiment/test/test_mmu_dcache.py
index 1fd58c07..1528d7d4 100644
--- a/src/soc/experiment/test/test_mmu_dcache.py
+++ b/src/soc/experiment/test/test_mmu_dcache.py
@@ -22,13 +22,20 @@ from soc.experiment.mmu import MMU
 from soc.experiment.dcache import DCache
 from soc.experiment.icache import ICache
 
-from random import randint
+import random
 
 stop = False
 
+def set_stop(newval):
+    global stop
+    stop = newval
+
+
 def b(x):
     return int.from_bytes(x.to_bytes(8, byteorder='little'),
                           byteorder='big', signed=False)
+
+
 default_mem = { 0x10000:    # PARTITION_TABLE_2
                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
                 b(0x800000000100000b),
@@ -52,14 +59,17 @@ def wb_get(c, mem, name):
     """simulator process for getting memory load requests
     """
 
-    global stop
-
+    logfile = open("/tmp/wb_get.log","w")
 
-    mem = mem
+    def log(msg):
+        logfile.write(msg+"\n")
+        print(msg)
 
+    global stop
     while not stop:
         while True: # wait for dc_valid
             if stop:
+                log("stop")
                 return
             cyc = yield (c.wb_out.cyc)
             stb = yield (c.wb_out.stb)
@@ -68,17 +78,18 @@ def wb_get(c, mem, name):
             yield
         addr = (yield c.wb_out.adr) << 3
         if addr not in mem:
-            print ("    %s LOOKUP FAIL %x" % (name, addr))
+            log("%s LOOKUP FAIL %x" % (name, addr))
             stop = True
             return
 
         yield
         data = mem[addr]
         yield c.wb_in.dat.eq(data)
-        print ("    %s get %x data %x" % (name, addr, data))
+        log("%s get %x data %x" % (name, addr, data))
         yield c.wb_in.ack.eq(1)
         yield
         yield c.wb_in.ack.eq(0)
+        yield
 
 
 def icache_sim(dut, mem):
@@ -102,47 +113,53 @@ def icache_sim(dut, mem):
         yield
         yield i_out.req.eq(1)
         yield i_out.nia.eq(C(k, 64))
-        for i in range(30):
+        while True:
             yield
-        yield
-        valid = yield i_in.valid
+            valid = yield i_in.valid
+            if valid:
+                break
         nia   = yield i_out.nia
         insn  = yield i_in.insn
-        print(f"valid? {valid}")
-        assert valid
+        yield
         assert insn == v, \
             "insn @%x=%x expected %x" % (nia, insn, v)
         yield i_out.req.eq(0)
         yield
 
 
-def test_icache():
-    dut    = ICache()
-    vl     = rtlil.convert(dut, ports=[])
+def test_icache_il():
+    dut = ICache()
+    vl = rtlil.convert(dut, ports=[])
     with open("test_icache.il", "w") as f:
         f.write(vl)
 
-    icache = ICache()
-
-    mem    = {}
-
-    for i in range(100):
-        mem[randint(0,1<<64)] = b(randint(0,1<<64))
-
-    m      = Module()
 
+def test_icache():
+    # create a random set of addresses and "instructions" at those addresses
+    mem = {}
+    # fail 'AssertionError: insn @1d8=0 expected 61928a6100000000'
+    #random.seed(41)
+    # fail infinite loop 'cache read adr: 24 data: 0'
+    random.seed(43)
+    for i in range(3):
+        mem[random.randint(0, 1<<10)] = b(random.randint(0,1<<32))
+
+    # set up module for simulation
+    m = Module()
+    icache = ICache()
     m.submodules.icache = icache
 
-
     # nmigen Simulation
     sim = Simulator(m)
     sim.add_clock(1e-6)
 
+    # read from "memory" process and corresponding wishbone "read" process
     sim.add_sync_process(wrap(icache_sim(icache, mem)))
     sim.add_sync_process(wrap(wb_get(icache, mem, "ICACHE")))
     with sim.write_vcd('test_icache.vcd'):
         sim.run()
 
+
 def mmu_lookup(mmu, addr):
     global stop
 
@@ -171,6 +188,7 @@ def mmu_lookup(mmu, addr):
 
     return phys_addr
 
+
 def mmu_sim(mmu):
     global stop
     yield mmu.rin.prtbl.eq(0x1000000) # set process table
@@ -184,6 +202,7 @@ def mmu_sim(mmu):
 
     stop = True
 
+
 def test_mmu():
     mmu = MMU()
     dcache = DCache()
@@ -204,6 +223,8 @@ def test_mmu():
     with sim.write_vcd('test_mmu.vcd'):
         sim.run()
 
+
 if __name__ == '__main__':
     test_mmu()
-#    test_icache()
+    #test_icache_il()
+    #test_icache()