X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Falu%2Fpipe_data.py;h=71363049ba5a437a708e53dfbc3370f17aa394d1;hp=3d64de891870a2580a3cbd5a34484d2ade10b93d;hb=HEAD;hpb=407f41392acaec1902e75cde2953c9c8f5d0692c

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index 3d64de89..572ec9a6 100644
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -1,94 +1,38 @@
-from nmigen import Signal, Const
-from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.fu.alu.alu_input_record import CompALUOpSubset
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.decoder.power_decoder2 import Data
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
 
-class IntegerData:
 
+class ALUInputData(FUBaseData):
     def __init__(self, pspec):
-        self.ctx = FPPipeContext(pspec)
-        self.muxid = self.ctx.muxid
+        super().__init__(pspec, False)
+        # convenience
+        self.a, self.b = self.ra, self.rb
 
-    def __iter__(self):
-        yield from self.ctx
+    @property
+    def regspec(self):
+        return [('INT', 'ra', self.intrange),  # RA
+               ('INT', 'rb', self.intrange),  # RB/immediate
+               ('XER', 'xer_so', '32'),  # XER bit 32: SO
+               ('XER', 'xer_ca', '34,45')]  # XER bit 34/45: CA/CA32
 
-    def eq(self, i):
-        return [self.ctx.eq(i.ctx)]
 
-    def ports(self):
-        return self.ctx.ports()
 
-
-class ALUInputData(IntegerData):
-    regspec = [('INT', 'a', '0:63'),
-               ('INT', 'b', '0:63'),
-               ('XER', 'xer_so', '32'),
-               ('XER', 'xer_ca', '34,45')]
+class ALUOutputData(FUBaseData):
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.a = Signal(64, reset_less=True) # RA
-        self.b = Signal(64, reset_less=True) # RB/immediate
-        self.xer_so = Signal(reset_less=True) # XER bit 32: SO
-        self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
-
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.a
-        yield self.b
-        yield self.xer_ca
-        yield self.xer_so
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.a.eq(i.a), self.b.eq(i.b),
-                      self.xer_ca.eq(i.xer_ca),
-                      self.xer_so.eq(i.xer_so)]
-
-# TODO: ALUIntermediateData which does not have
-# cr0, ov, ov32 in it (because they are generated as outputs by
-# the final output stage, not by the intermediate stage)
-# https://bugs.libre-soc.org/show_bug.cgi?id=305#c19
-
-class ALUOutputData(IntegerData):
-    regspec = [('INT', 'o', '0:63'),
-               ('CR', 'cr0', '0:3'),
-               ('XER', 'xer_ca', '34,45'),
-               ('XER', 'xer_ov', '33,44'),
+        super().__init__(pspec, True)
+        # convenience
+        self.cr0 = self.cr_a
+
+    @property
+    def regspec(self):
+        return [('INT', 'o', self.intrange),
+               ('CR', 'cr_a', '0:3'),
+               ('XER', 'xer_ca', '34,45'),  # bit0: ca, bit1: ca32
+               ('XER', 'xer_ov', '33,44'),  # bit0: ov, bit1: ov32
                ('XER', 'xer_so', '32')]
-    def __init__(self, pspec):
-        super().__init__(pspec)
-        self.o = Signal(64, reset_less=True, name="stage_o")
-        self.cr0 = Data(4, name="cr0")
-        self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
-        self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
-        self.xer_so = Data(1, name="xer_so")
-
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.xer_ca
-        yield self.cr0
-        yield self.xer_ov
-        yield self.xer_so
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.o.eq(i.o),
-                      self.xer_ca.eq(i.xer_ca),
-                      self.cr0.eq(i.cr0),
-                      self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)]
-
 
-class IntPipeSpec:
-    def __init__(self, id_wid=2, op_wid=1):
-        self.id_wid = id_wid
-        self.op_wid = op_wid
-        self.opkls = lambda _: CompALUOpSubset(name="op")
-        self.stage = None
 
 
-class ALUPipeSpec(IntPipeSpec):
-    def __init__(self, id_wid, op_wid):
-        super().__init__(id_wid, op_wid)
-        self.pipekls = SimpleHandshakeRedir
+class ALUPipeSpec(CommonPipeSpec):
+    opsubsetkls = CompALUOpSubset
+    regspecklses = (ALUInputData, ALUOutputData)