X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Ftest%2Fcommon.py;h=1143e8958fc642ebbd7de80299b3c7f9f149e9ba;hp=bd0e948effb75d9c37cb63103b87679bdb25e1b3;hb=f8dfa2c982addbde7776dbfddc87d2b8c3e247eb;hpb=8df8b77506af4bb609e821719b0ca42f2e72aefc

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index bd0e948e..1143e895 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -257,16 +257,16 @@ class ALUHelpers:
         if ok:
             spr_num = yield dec2.e.write_fast2.data
             spr_num = fast_reg_to_spr(spr_num)
-            spr_name = spr_dict[spr_num]
-            res['fast2'] = sim.spr[spr_name]
+            spr_name = spr_dict[spr_num].SPR
+            res['fast2'] = sim.spr[spr_name].value
 
     def get_wr_fast_spr1(res, sim, dec2):
         ok = yield dec2.e.write_fast1.ok
         if ok:
             spr_num = yield dec2.e.write_fast1.data
             spr_num = fast_reg_to_spr(spr_num)
-            spr_name = spr_dict[spr_num]
-            res['fast1'] = sim.spr[spr_name]
+            spr_name = spr_dict[spr_num].SPR
+            res['fast1'] = sim.spr[spr_name].value
 
     def get_wr_sim_xer_ca(res, sim, dec2):
         cry_out = yield dec2.e.output_carry