X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=blobdiff_plain;f=src%2Fsoc%2Fsv%2Ftrans%2Fsvp64.py;h=2e54f708580d6bcfd123c57a6403d14e7249c775;hp=0cb14a78d900d99cb8a864de80af77dd7f17d32e;hb=b4e7b078e09220acd49bbaa84c1280630b7d10e4;hpb=1f7f510c9b03d3646a52153874b37f33062b9ae5

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index 0cb14a78..2e54f708 100644
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -18,7 +18,7 @@ import os, sys
 from collections import OrderedDict
 
 from soc.decoder.pseudo.pagereader import ISA
-from soc.decoder.power_enums import get_csv, find_wiki_dir
+from soc.decoder.power_svp64 import SVP64RM
 
 
 # identifies register by type
@@ -129,16 +129,6 @@ def decode_ffirst(encoding):
     return decode_bo(encoding)
 
 
-# gets SVP64 ReMap information
-class SVP64RM:
-    def __init__(self):
-        self.instrs = {}
-        pth = find_wiki_dir()
-        for fname in os.listdir(pth):
-            if fname.startswith("RM") or fname.startswith("LDSTRM"):
-                for entry in get_csv(fname):
-                    self.instrs[entry['insn']] = entry
-
 
 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 class SVP64: