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(parent: f6e1cf7) | patch
Fix incorrect signal widths
authorCesar Strauss <cestrauss@gmail.com>
Fri, 15 Apr 2022 19:36:05 +0000 (16:36 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Fri, 15 Apr 2022 19:36:05 +0000 (16:36 -0300)
commit11de641fb71cd6939d5f67d367865d6ac3f3220d
tree50bede72a6a7e013187285cfe6553239a3b85d27tree
parentf6e1cf7faa8d95f12e6218e5fdaa19acd633f734commit | diff
Fix incorrect signal widths

dbg_data is the width of a write lane (granularity) and dbg_wrote is a
single bit.
src/soc/regfile/sram_wrapper.py diff | blob | history