ha! have to explicitly specify the ports when writing out to ilang or verilog
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 30 Jul 2020 12:27:55 +0000 (13:27 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 30 Jul 2020 12:27:55 +0000 (13:27 +0100)
commit2b8032ccc332af27614b4e90db20f8f6c64ec361
tree5e53622130c5cbac05f9fb41e81edcf76861f75c
parent38c5f0052e7922ebdc680a24559029f353ec5b5d
ha! have to explicitly specify the ports when writing out to ilang or verilog
this gives unused signals that default to a non-zero value to inherently
set by default to that value.
exposing them externally via ports makes setting them the *users*
src/soc/experiment/l0_cache.py
src/soc/simple/issuer.py
src/soc/simple/issuer_verilog.py