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(parent: f10c64c) | patch
enable I-Cache wishbone memory type in issuer_verilog.py if MMU requested
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 21 Dec 2021 16:32:55 +0000 (16:32 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 21 Dec 2021 16:32:55 +0000 (16:32 +0000)
commit2d386cfefd991ca19d6b59b08e09a56c2e82886f
tree28d5abab34f6ea25b9afc306119987f0646aa056tree
parentf10c64c74530eb6400136e73648f5d31e6da092acommit | diff
enable I-Cache wishbone memory type in issuer_verilog.py if MMU requested
src/soc/simple/issuer_verilog.py diff | blob | history