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(parent: 521ed07) | patch
litex/florent/versa_ecp5.py add arg --fpga [versa_ecp5|ulx3s85f] default
authorCole Poirier <colepoirier@gmail.com>
Mon, 12 Oct 2020 23:30:10 +0000 (16:30 -0700)
committerCole Poirier <colepoirier@gmail.com>
Mon, 12 Oct 2020 23:30:10 +0000 (16:30 -0700)
commit364e953f8b197830c4dc0a8f7c69713df416e66f
treeda4509bb8e25d995f01b6bec8a89b8713c76c2fetree
parent521ed071b614c4835461749890e13ce824d79ac2commit | diff
litex/florent/versa_ecp5.py add arg --fpga [versa_ecp5|ulx3s85f] default
of versa_ecp5, to build for different fpga targets, fix whitespace,
delete ulx3s85f.py as it's no longer needed
src/soc/litex/florent/ulx3s85f.py [deleted file] blob | history
src/soc/litex/florent/versa_ecp5.py diff | blob | history