add bit-wise OR and AND
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 3 Apr 2020 15:12:56 +0000 (16:12 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 3 Apr 2020 15:12:56 +0000 (16:12 +0100)
commit39c8314f9a14fb5351a9dcbc8bd37753bdcd0fee
tree1a2216a4d959de9261cd520e3d828c16fa0cc678
parent7719f0a001bf74a78d541fd04fb3ca9752f1851c
add bit-wise OR and AND
libreriscv
src/soc/decoder/power_pseudo.py
src/soc/decoder/pseudo/lexer.py
src/soc/decoder/pseudo/parser.py
src/soc/decoder/selectable_int.py