reduce clkcsel ls180 width (2 pins), rename pll_18 signal
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 13 Nov 2020 17:47:46 +0000 (17:47 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 13 Nov 2020 17:47:46 +0000 (17:47 +0000)
commit3dce9e7342e15c491ecc0bdb3acf90e2987dd0b3
tree1cf7241d4035a276266a2da265fe37aff97c76ef
parente8a73e28939598ec2b7d1b4c6c73cef4afb93e07
reduce clkcsel ls180 width (2 pins), rename pll_18 signal
src/soc/clock/dummypll.py
src/soc/litex/florent/libresoc/core.py
src/soc/litex/florent/libresoc/ls180.py
src/soc/simple/issuer.py