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(parent: d6604a7) | patch
add external core verilog wrapper, ironically around Libre-SOC
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 14 Feb 2022 13:08:56 +0000 (13:08 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 14 Feb 2022 13:08:56 +0000 (13:08 +0000)
commit3f56fbaf59bd43792bc88e6d633758ab296ded87
treead597cc472c0283ad8fbf62ac6d3741b9694e954tree
parentd6604a7f7abdd0e36eebc3bd8b9e822143aba500commit | diff
add external core verilog wrapper, ironically around Libre-SOC
(as well as Microwatt)
src/soc/bus/external_core.py [new file with mode: 0644] blob