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(parent: e7de0b2) | patch
bool test on traptype to
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 24 Jan 2022 11:58:03 +0000 (11:58 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 24 Jan 2022 11:58:03 +0000 (11:58 +0000)
commit4c91ccb579fe45712133572a33e2bd57cb184236
treec9a64fe93edf994ebaa3cc69aa9ab4fa24979daftree
parente7de0b277f0c88990eafcdfac9292037120a94facommit | diff
bool test on traptype to
ensure two conditions are properly ANDed
also copy correct bits of SRR over, but there is an additional
bug here that needs to be fixed: Exception class needs to pass over
the bottom 16 LSBs of SRR1
src/soc/fu/trap/main_stage.py diff | blob | history