add wishbone sram.py (move from nmigen-soc)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 20 Apr 2021 14:34:34 +0000 (15:34 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 20 Apr 2021 14:34:34 +0000 (15:34 +0100)
commit5335aad7de728afb53e4fe89fe93fbccbdee1cff
tree9e1498a275cefaed31379f1a81835b03da401105
parentad4fb0e1da6662768da85bb2941a883d4c0bb69e
add wishbone sram.py (move from nmigen-soc)
src/soc/bus/sram.py [new file with mode: 0644]