add XICS memory regions, shrink litex CSR memmap size to do it
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 4 Sep 2020 19:48:30 +0000 (20:48 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 4 Sep 2020 19:48:30 +0000 (20:48 +0100)
commit5ce5507af3cfb53c1e8f0417dc754172492bbe6e
tree432d8a07abfb4409c662978f3b2bc62ad55011db
parentd006bf31cce8c550ea7dc2d638ee49b8c8436a8d
add XICS memory regions, shrink litex CSR memmap size to do it
src/soc/litex/florent/libresoc/core.py
src/soc/litex/florent/sim.py