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(parent: be0071c) | patch
icache.py add some missing lines from icache.vhdl, add sram for sim, fix
authorCole Poirier <colepoirier@gmail.com>
Thu, 24 Sep 2020 19:15:20 +0000 (12:15 -0700)
committerCole Poirier <colepoirier@gmail.com>
Thu, 24 Sep 2020 19:15:20 +0000 (12:15 -0700)
commit5f4e40f1ea43cc60c9114e4b0fed1a65bae2937f
treeb81240dedee6bb99ab9b15aaed1bdbc1d0b8bccatree
parentbe0071c08a65bf9ff700dd5019c03b82c733ffa5commit | diff
icache.py add some missing lines from icache.vhdl, add sram for sim, fix
bug due to main state machine being indednted one level to far an thus
not triggered properly
src/soc/experiment/icache.py diff | blob | history