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(parent: a5bd4d6) | patch
add signal for pausing the DEC/TB FSM to IssuerBase
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 17 Jan 2022 11:50:50 +0000 (11:50 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 17 Jan 2022 11:50:50 +0000 (11:50 +0000)
commit5fb659041e7ef39cc469943422e154cb4223aa1a
tree949f2cb9952fbcb7172662a9c4f16d7447772ac2tree
parenta5bd4d6324e1c72a8e1e8874962aad6246061676commit | diff
add signal for pausing the DEC/TB FSM to IssuerBase
there is a potential issue with the DEC SPR that needs solving,
and there is a race condition where an mtspr DEC/TB could get
overwritten
adding a "pause" mechanism to the FSM should solve that
src/soc/simple/issuer.py diff | blob | history