add simple GPIO wishbone bus to litex sim.py
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Sep 2020 14:03:21 +0000 (15:03 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Sep 2020 14:03:21 +0000 (15:03 +0100)
commit63ccd4c6351103b904a956b7963cf42f53e748ca
treeca9a06c5f86afc9e4468de39680e0bbac48ffea9
parent16598f451a219b36f01ac8ddc11b6417422fc430
add simple GPIO wishbone bus to litex sim.py
src/soc/bus/simple_gpio.py
src/soc/litex/florent/libresoc/core.py
src/soc/litex/florent/sim.py
src/soc/simple/issuer_verilog.py