make Memory accessible via TestSRAMBareLoadStoreUnit
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 27 Jun 2020 19:21:12 +0000 (20:21 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 27 Jun 2020 19:21:12 +0000 (20:21 +0100)
commit65ad441b8a6aa9fc4a1756e19e3f702c9e1a7f98
tree02eb34b4b5f60a437550b832deef3960cb8ae6c7
parent8e3fd4d0be5cba1ebc530858786a81136e8c6271
make Memory accessible via TestSRAMBareLoadStoreUnit
src/soc/bus/test/test_minerva.py
src/soc/fu/compunits/test/test_compunit.py