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(parent: f8e6f7e) | patch
Remove extra yield from test case.
authorCesar Strauss <cestrauss@gmail.com>
Mon, 20 Jul 2020 20:13:27 +0000 (17:13 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Mon, 20 Jul 2020 20:13:27 +0000 (17:13 -0300)
commit67a04feb918521da7e4ca7e07f8605507ee0e761
tree791cd7a3235f32a1b41baa3b715636929015997etree
parentf8e6f7e0ba089e57c9c2baade2e8add647e43ff6commit | diff
Remove extra yield from test case.

Seems pysim is correct, after all. There seems to be some
strange interaction between cxxrtl and python.
src/soc/experiment/alu_fsm.py diff | blob | history