create signal on test_issuer which gives PLL clk_sel_i a useful name
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 18 Apr 2021 20:27:30 +0000 (21:27 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 18 Apr 2021 20:27:30 +0000 (21:27 +0100)
commit6d77ed4073220e75fc10b99daebc6e0946190c02
tree6cc6da6ce0df126a856b50cc523892058d1c7058
parentde23e67f13c0b828850d39d99a1f989dea6942fa
create signal on test_issuer which gives PLL clk_sel_i a useful name
src/soc/clock/dummypll.py
src/soc/simple/issuer.py