noticed the regular pattern in all pipe_data.py (regspecs).
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 6 Jun 2020 04:38:09 +0000 (05:38 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 6 Jun 2020 04:38:09 +0000 (05:38 +0100)
commit87561eb392c5c7cc0cea1bc6ec6012209b9c94fb
tree8043def3a7e7e2c1648b00e23a3f7171f105c90a
parentd7c57c430d8ecba6ad775abc12edd8ef6b4ba8d7
noticed the regular pattern in all pipe_data.py (regspecs).
removed manual Input/Output Data, use regspecs to create it, in IntegerData
src/soc/fu/alu/pipe_data.py
src/soc/fu/branch/pipe_data.py
src/soc/fu/cr/pipe_data.py
src/soc/fu/ldst/pipe_data.py
src/soc/fu/logical/pipe_data.py
src/soc/fu/pipe_data.py
src/soc/fu/regspec.py
src/soc/fu/shift_rot/pipe_data.py
src/soc/fu/spr/pipe_data.py
src/soc/fu/trap/pipe_data.py