get litex sim enabled with 32-bit wishbone bus
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 21 Aug 2020 15:37:10 +0000 (16:37 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 21 Aug 2020 15:37:10 +0000 (16:37 +0100)
commitc83043ee58e86a1b1da7b76a2b2d34e1667923dc
treeb9824ff19f752193550f5367442a1fd900fa1b51
parent6ad0d585bfc28106f1fbea3273513add4a4fa1c6
get litex sim enabled with 32-bit wishbone bus
src/soc/litex/florent/libresoc/core.py
src/soc/litex/florent/sim.py
src/soc/minerva/units/loadstore.py
src/soc/simple/issuer.py
src/soc/simple/issuer_verilog.py
src/soc/simple/test/test_issuer.py