pass in msr_reset to issuer_verilog.py
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 23 Dec 2021 16:57:59 +0000 (16:57 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 23 Dec 2021 16:57:59 +0000 (16:57 +0000)
commite143a6750feb38427cfd53aa011ec07343f53a0c
tree697a2c51305a1fc735e0fd717c8b7b26b5a5ce1b
parent79d09c90765b810424a735a60829abbb4b7a2ce2
pass in msr_reset to issuer_verilog.py
src/soc/simple/issuer_verilog.py