projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 89210d0) | patch
connect up LD to memory: set transparent mode to False.
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 9 Mar 2020 16:28:45 +0000 (16:28 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 9 Mar 2020 16:28:45 +0000 (16:28 +0000)
commiteca80986a909280f7ebce025c32040cc440d2e3c
treed1298650491eba7d5d578e547fba073ba0ce7a3ctree
parent89210d00fea0429d0193efd9250c8ed2b07a9a53commit | diff
connect up LD to memory: set transparent mode to False.
need to check if the memory is valid one clock later
src/soc/experiment/compldst.py diff | blob | history
src/soc/experiment/testmem.py diff | blob | history