git.libre-soc.org Git - soc.git/commit

author	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Sun, 27 Feb 2022 18:17:08 +0000 (18:17 +0000)
committer	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Sun, 27 Feb 2022 18:17:08 +0000 (18:17 +0000)
commit	fb3528750f912a762984a79654cce6601c52a994
tree	4ff7210cddd0fa12c34cd17280a5b7a66fd14dbd	tree
parent	32b2120c0bd42fcf2c15e7f93df7efb76bb8b835	commit \| diff

convert from public static functions/properties for regspecs
to member functions to obtain regspecs
this allows pspec (containing XLEN) to be passed to the regspecs,
which in turn allows them to be dynamically set by issuer_verilog.py
and unit tests

14 files changed:

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src/soc/fu/alu/pipe_data.py		diff \| blob \| history
src/soc/fu/branch/pipe_data.py		diff \| blob \| history
src/soc/fu/compunits/compunits.py		diff \| blob \| history
src/soc/fu/cr/pipe_data.py		diff \| blob \| history
src/soc/fu/div/pipe_data.py		diff \| blob \| history
src/soc/fu/ldst/pipe_data.py		diff \| blob \| history
src/soc/fu/logical/pipe_data.py		diff \| blob \| history
src/soc/fu/mmu/pipe_data.py		diff \| blob \| history
src/soc/fu/mul/pipe_data.py		diff \| blob \| history
src/soc/fu/pipe_data.py		diff \| blob \| history
src/soc/fu/regspec.py		diff \| blob \| history
src/soc/fu/shift_rot/pipe_data.py		diff \| blob \| history
src/soc/fu/spr/pipe_data.py		diff \| blob \| history
src/soc/fu/trap/pipe_data.py		diff \| blob \| history