move dmi_sim to separate module

diff --git a/src/soc/debug/test/dmi_sim.py b/src/soc/debug/test/dmi_sim.py
new file mode 100644 (file)
index 0000000..c0d376d
--- /dev/null
+++ b/src/soc/debug/test/dmi_sim.py
@@ -0,0 +1,45 @@
+"""DMI "simulator" process for nmigen tests
+"""
+
+from soc.debug.dmi import  DBGCore
+
+def dmi_sim(dut):
+
+    ctrl_reg = 0b100 # terminated
+
+    dmi = dut.dmi
+    while not dut.stop:
+        # wait for req
+        req = yield dmi.req_i
+        if req == 0:
+            yield
+            continue
+
+        # check read/write and address
+        wen = yield dmi.we_i
+        addr = yield dmi.addr_i
+        print ("        dmi wen, addr", wen, addr)
+        if addr == DBGCore.CTRL and wen == 0:
+            print ("        read ctrl reg", ctrl_reg)
+            yield dmi.dout.eq(ctrl_reg)
+            yield dmi.ack_o.eq(1)
+            yield
+            yield dmi.ack_o.eq(0)
+        elif addr == DBGCore.CTRL and wen == 1:
+            ctrl_reg = (yield dmi.din)
+            print ("        write ctrl reg", ctrl_reg)
+            yield dmi.ack_o.eq(1)
+            yield
+            yield dmi.ack_o.eq(0)
+        elif addr == DBGCore.MSR and wen == 0:
+            print ("        read msr reg")
+            yield dmi.dout.eq(0xdeadbeef) # test MSR value
+            yield dmi.ack_o.eq(1)
+            yield
+            yield dmi.ack_o.eq(0)
+        else:
+            # do nothing but just ack it
+            yield dmi.ack_o.eq(1)
+            yield
+            yield dmi.ack_o.eq(0)
+

diff --git a/src/soc/debug/test/test_jtag_tap.py b/src/soc/debug/test/test_jtag_tap.py
index ca904d4aa03cb40a843c259081fb444fdc731287..8c88271bc43394710aefce69c65465bc71d38624 100644 (file)
--- a/src/soc/debug/test/test_jtag_tap.py
+++ b/src/soc/debug/test/test_jtag_tap.py
@@ -5,7 +5,8 @@ based on Staf Verhaegen (Chips4Makers) wishbone TAP
 
 from nmigen import (Module, Signal, Elaboratable, Const)
 from c4m.nmigen.jtag.tap import TAP, IOType
-from soc.debug.dmi import  DMIInterface, DBGCore
+from soc.debug.dmi import DMIInterface, DBGCore
+from soc.debug.test.dmi_sim import dmi_sim
 from soc.debug.dmi2jtag import DMITAP
 
 from nmigen_soc.wishbone.sram import SRAM
@@ -69,49 +70,6 @@ def jtag_read_write_reg(dut, addr, d_len, d_in=0):
     return result
 
 
-stop = False
-
-def dmi_sim(dut):
-    global stop
-
-    ctrl_reg = 0b100 # terminated
-
-    dmi = dut.dmi
-    while not stop:
-        # wait for req
-        req = yield dmi.req_i
-        if req == 0:
-            yield
-            continue
-
-        # check read/write and address
-        wen = yield dmi.we_i
-        addr = yield dmi.addr_i
-        print ("        dmi wen, addr", wen, addr)
-        if addr == DBGCore.CTRL and wen == 0:
-            print ("        read ctrl reg", ctrl_reg)
-            yield dmi.dout.eq(ctrl_reg)
-            yield dmi.ack_o.eq(1)
-            yield
-            yield dmi.ack_o.eq(0)
-        elif addr == DBGCore.CTRL and wen == 1:
-            ctrl_reg = (yield dmi.din)
-            print ("        write ctrl reg", ctrl_reg)
-            yield dmi.ack_o.eq(1)
-            yield
-            yield dmi.ack_o.eq(0)
-        elif addr == DBGCore.MSR and wen == 0:
-            print ("        read msr reg")
-            yield dmi.dout.eq(0xdeadbeef) # test MSR value
-            yield dmi.ack_o.eq(1)
-            yield
-            yield dmi.ack_o.eq(0)
-        else:
-            # do nothing but just ack it
-            yield dmi.ack_o.eq(1)
-            yield
-            yield dmi.ack_o.eq(0)
-
 # JTAG-ircodes for accessing DMI
 DMI_ADDR = 5
 DMI_READ = 6
@@ -185,12 +143,12 @@ def jtag_sim(dut):
 
     ####### done - tell dmi_sim to stop (otherwise it won't) ########
 
-    global stop
-    stop = True
+    dut.stop = True
 
 
 if __name__ == '__main__':
     dut = DMITAP(ir_width=4)
+    dut.stop = False
     iotypes = (IOType.In, IOType.Out, IOType.TriOut, IOType.InTriOut)
     ios = [dut.add_io(iotype=iotype) for iotype in iotypes]
     dut.sr = dut.add_shiftreg(ircode=4, length=3) # test loopback register

diff --git a/src/soc/litex/florent/openocd.cfg b/src/soc/litex/florent/openocd.cfg
index a3c7084a01aef9ffed34c1f2a4ba06df4d688a31..9cd40c3a4af07e93d17a908313ca598f982d85b0 100644 (file)
--- a/src/soc/litex/florent/openocd.cfg
+++ b/src/soc/litex/florent/openocd.cfg
@@ -6,8 +6,8 @@ remote_bitbang_host localhost
 # this should be irlen=4
 jtag newtap libresoc tap -irlen 4 -irmask 0xf -ircapture 0xf -expected-id 0x000018ff
 
-#set _TARGETNAME libresoc.tap
-#target create $_TARGETNAME.0 ppc64 -chain-position $_TARGETNAME -rtos hwthread
+set _TARGETNAME libresoc.tap
+target create $_TARGETNAME.0 ppc64 -chain-position $_TARGETNAME -rtos hwthread
 
 # Configure work area in on-chip SRAM
 #$_TARGETNAME.0 configure -work-area-phys 0x80000000 \

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 332dda805ebbbf3f9bbfe507853db47042a1699a..4582e4ec3327bf95a4fdabbbea3b1e571f5f3869 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -117,6 +117,8 @@ class TestIssuer(Elaboratable):
         m.submodules.dbg = dbg = self.dbg
         if self.jtag_en:
             m.submodules.jtag = jtag = self.jtag
+            # TODO: UART2GDB mux, here, from external pin
+            # see https://bugs.libre-soc.org/show_bug.cgi?id=499
             comb += dbg.dmi.connect_to(jtag.dmi)
 
         cur_state = self.cur_state