testcase fo mulli

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index f356dd768105c98f56814581b09956a9e17b9928..0a26380cd996d20f4bd65585bc1bbcea257bd5bc 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -115,6 +115,13 @@ class DecoderTestCase(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1])
 
+    def test_mulli(self):
+        lst = ["addi 1, 0, 3",
+               "mulli 1, 1, 2"
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1])
+
     def run_tst_program(self, prog, reglist):
         simulator = InternalOpSimulator()
         self.run_tst(prog, simulator)