Reminder for a possible hardware optimization

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 5101ecb20737f5b6965a9c05d3bdd4b321b892d5..0bfbcd3ccc7181f6d5cfdd80c655eb1cdf06d11e 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -607,6 +607,8 @@ class TestIssuerInternal(Elaboratable):
                         comb += skip_srcstep.eq(cur_srcstep + src_delta)
                         # shift-out all leading zeros from the mask
                         # plus the leading "one" bit
+                        # TODO count leading zeros and shift-out the zero
+                        #      bits, in the same step, in hardware
                         sync += self.srcmask.eq(self.srcmask >> (src_delta+1))
 
                         # same as above, but for dststep