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convert to individual PipeSpecs for each pipeline
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 21 May 2020 10:33:58 +0000
(11:33 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 21 May 2020 10:33:58 +0000
(11:33 +0100)
src/soc/fu/alu/pipe_data.py
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src/soc/fu/alu/test/test_pipe_caller.py
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src/soc/fu/branch/pipe_data.py
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src/soc/fu/branch/test/test_pipe_caller.py
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src/soc/fu/cr/pipe_data.py
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src/soc/fu/cr/test/test_pipe_caller.py
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src/soc/fu/logical/pipe_data.py
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src/soc/fu/logical/test/test_pipe_caller.py
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diff --git
a/src/soc/fu/alu/pipe_data.py
b/src/soc/fu/alu/pipe_data.py
index 7aa2fed2885ea32c154feec85979be72067d5281..32e2944a3fb1a092c59d0b9772d07110013e4c46 100644
(file)
--- a/
src/soc/fu/alu/pipe_data.py
+++ b/
src/soc/fu/alu/pipe_data.py
@@
-77,16
+77,12
@@
class ALUOutputData(IntegerData):
self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)]
self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)]
-class IntPipeSpec:
- def __init__(self, id_wid=2, op_wid=1):
- self.id_wid = id_wid
- self.op_wid = op_wid
- self.opkls = lambda _: CompALUOpSubset(name="op")
- self.stage = None
-
-
-class ALUPipeSpec(IntPipeSpec):
+class ALUPipeSpec:
regspec = (ALUInputData.regspec, ALUOutputData.regspec)
regspec = (ALUInputData.regspec, ALUOutputData.regspec)
+ opsubsetkls = CompALUOpSubset
def __init__(self, id_wid, op_wid):
def __init__(self, id_wid, op_wid):
- super().__init__(id_wid, op_wid)
self.pipekls = SimpleHandshakeRedir
self.pipekls = SimpleHandshakeRedir
+ self.id_wid = id_wid
+ self.op_wid = op_wid
+ self.opkls = lambda _: self.opsubsetkls(name="op")
+ self.stage = None
diff --git
a/src/soc/fu/alu/test/test_pipe_caller.py
b/src/soc/fu/alu/test/test_pipe_caller.py
index 875bfab43bcea61ee85e94fe28d7b3b3ee4458cf..dbdb4f6e4acf24dba36a1a4a72f449f71ab6a3fb 100644
(file)
--- a/
src/soc/fu/alu/test/test_pipe_caller.py
+++ b/
src/soc/fu/alu/test/test_pipe_caller.py
@@
-163,7
+163,7
@@
class ALUTestCase(FHDLTestCase):
self.run_tst_program(Program(lst), initial_regs, {})
def test_ilang(self):
self.run_tst_program(Program(lst), initial_regs, {})
def test_ilang(self):
- rec =
CompALUOpSubset
()
+ rec =
ALUPipeSpec.opsubsetkls
()
pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
alu = ALUBasePipe(pspec)
pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
alu = ALUBasePipe(pspec)
@@
-186,7
+186,7
@@
class TestRunner(FHDLTestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec =
CompALUOpSubset
()
+ rec =
ALUPipeSpec.opsubsetkls
()
pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
m.submodules.alu = alu = ALUBasePipe(pspec)
pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
m.submodules.alu = alu = ALUBasePipe(pspec)
diff --git
a/src/soc/fu/branch/pipe_data.py
b/src/soc/fu/branch/pipe_data.py
index e75f9e966c70876a089d5093a743b24e3e54b1c2..153f9bf03c5e4cb4a07185625ef816e9c1a9daf6 100644
(file)
--- a/
src/soc/fu/branch/pipe_data.py
+++ b/
src/soc/fu/branch/pipe_data.py
@@
-30,6
+30,7
@@
from soc.fu.alu.pipe_data import IntegerData
from nmutil.dynamicpipe import SimpleHandshakeRedir
from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
from nmutil.dynamicpipe import SimpleHandshakeRedir
from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
+
class BranchInputData(IntegerData):
regspec = [('SPR', 'spr1', '0:63'),
('SPR', 'spr2', '0:63'),
class BranchInputData(IntegerData):
regspec = [('SPR', 'spr1', '0:63'),
('SPR', 'spr2', '0:63'),
@@
-92,9
+93,10
@@
class BranchOutputData(IntegerData):
# TODO: replace CompALUOpSubset with CompBranchOpSubset
class BranchPipeSpec:
regspec = (BranchInputData.regspec, BranchOutputData.regspec)
# TODO: replace CompALUOpSubset with CompBranchOpSubset
class BranchPipeSpec:
regspec = (BranchInputData.regspec, BranchOutputData.regspec)
+ opsubsetkls = CompALUOpSubset
def __init__(self, id_wid, op_wid):
self.id_wid = id_wid
self.op_wid = op_wid
def __init__(self, id_wid, op_wid):
self.id_wid = id_wid
self.op_wid = op_wid
- self.opkls = lambda _:
CompALUOpSubset
(name="op")
+ self.opkls = lambda _:
self.opsubsetkls
(name="op")
self.stage = None
self.pipekls = SimpleHandshakeRedir
self.stage = None
self.pipekls = SimpleHandshakeRedir
diff --git
a/src/soc/fu/branch/test/test_pipe_caller.py
b/src/soc/fu/branch/test/test_pipe_caller.py
index 53758b1df6839256da681e026d5bdda938fc30b6..75cac8090f561b80d86defbccf3fc05c77353755 100644
(file)
--- a/
src/soc/fu/branch/test/test_pipe_caller.py
+++ b/
src/soc/fu/branch/test/test_pipe_caller.py
@@
-13,7
+13,6
@@
from soc.decoder.isa.all import ISA
from soc.fu.branch.pipeline import BranchBasePipe
from soc.fu.branch.pipeline import BranchBasePipe
-from soc.fu.branch.br_input_record import CompBROpSubset
from soc.fu.branch.pipe_data import BranchPipeSpec
import random
from soc.fu.branch.pipe_data import BranchPipeSpec
import random
@@
-99,7
+98,7
@@
class BranchTestCase(FHDLTestCase):
initial_cr=cr)
def test_ilang(self):
initial_cr=cr)
def test_ilang(self):
- rec =
CompBROpSubset
()
+ rec =
BranchPipeSpec.opsubsetkls
()
pspec = BranchPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
alu = BranchBasePipe(pspec)
pspec = BranchPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
alu = BranchBasePipe(pspec)
@@
-122,7
+121,7
@@
class TestRunner(FHDLTestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec =
CompBROpSubset
()
+ rec =
BranchPipeSpec.opsubsetkls
()
pspec = BranchPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
m.submodules.branch = branch = BranchBasePipe(pspec)
pspec = BranchPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
m.submodules.branch = branch = BranchBasePipe(pspec)
diff --git
a/src/soc/fu/cr/pipe_data.py
b/src/soc/fu/cr/pipe_data.py
index a955cdad0ad1faacff2ba9eeb8866e62e47628c3..a6cd835e9b3886224d783227b973f04fec363b29 100644
(file)
--- a/
src/soc/fu/cr/pipe_data.py
+++ b/
src/soc/fu/cr/pipe_data.py
@@
-1,6
+1,8
@@
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.alu.pipe_data import IntegerData
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.alu.pipe_data import IntegerData
+from nmutil.dynamicpipe import SimpleHandshakeRedir
+from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
class CRInputData(IntegerData):
class CRInputData(IntegerData):
@@
-38,3
+40,14
@@
class CROutputData(IntegerData):
lst = super().eq(i)
return lst + [self.o.eq(i.o),
self.cr.eq(i.cr)]
lst = super().eq(i)
return lst + [self.o.eq(i.o),
self.cr.eq(i.cr)]
+
+# TODO: replace CompALUOpSubset with CompCROpSubset
+class CRPipeSpec:
+ regspec = (CRInputData.regspec, CROutputData.regspec)
+ opsubsetkls = CompALUOpSubset
+ def __init__(self, id_wid, op_wid):
+ self.id_wid = id_wid
+ self.op_wid = op_wid
+ self.opkls = lambda _: self.opsubsetkls(name="op")
+ self.stage = None
+ self.pipekls = SimpleHandshakeRedir
diff --git
a/src/soc/fu/cr/test/test_pipe_caller.py
b/src/soc/fu/cr/test/test_pipe_caller.py
index 415ce48e746e68e3a853299ae3e007974b089f2f..31da549669def3ebf89257607d095b3c2ff28161 100644
(file)
--- a/
src/soc/fu/cr/test/test_pipe_caller.py
+++ b/
src/soc/fu/cr/test/test_pipe_caller.py
@@
-14,7
+14,7
@@
from soc.decoder.isa.all import ISA
from soc.fu.cr.pipeline import CRBasePipe
from soc.fu.alu.alu_input_record import CompALUOpSubset
from soc.fu.cr.pipeline import CRBasePipe
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.fu.
alu.pipe_data import ALU
PipeSpec
+from soc.fu.
cr.pipe_data import CR
PipeSpec
import random
import random
@@
-117,9
+117,9
@@
class CRTestCase(FHDLTestCase):
def test_ilang(self):
def test_ilang(self):
- rec = C
ompALUOpSubset
()
+ rec = C
RPipeSpec.opsubsetkls
()
- pspec =
ALU
PipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec =
CR
PipeSpec(id_wid=2, op_wid=get_rec_width(rec))
alu = CRBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("cr_pipeline.il", "w") as f:
alu = CRBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("cr_pipeline.il", "w") as f:
@@
-149,9
+149,9
@@
class TestRunner(FHDLTestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec = C
ompALUOpSubset
()
+ rec = C
RPipeSpec.opsubsetkls
()
- pspec =
ALU
PipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec =
CR
PipeSpec(id_wid=2, op_wid=get_rec_width(rec))
m.submodules.alu = alu = CRBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
m.submodules.alu = alu = CRBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
diff --git
a/src/soc/fu/logical/pipe_data.py
b/src/soc/fu/logical/pipe_data.py
index 9ed7252f4c36715b0f061c83e575086bfeb482d9..256317cb62012c90ba4b865b1545786b872ca17b 100644
(file)
--- a/
src/soc/fu/logical/pipe_data.py
+++ b/
src/soc/fu/logical/pipe_data.py
@@
-1,6
+1,8
@@
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.alu.pipe_data import IntegerData
+from soc.fu.alu.pipe_data import IntegerData, ALUOutputData
+from nmutil.dynamicpipe import SimpleHandshakeRedir
+from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
class LogicalInputData(IntegerData):
class LogicalInputData(IntegerData):
@@
-27,3
+29,15
@@
class LogicalInputData(IntegerData):
return lst + [self.a.eq(i.a), self.b.eq(i.b),
self.xer_ca.eq(i.xer_ca),
self.xer_so.eq(i.xer_so)]
return lst + [self.a.eq(i.a), self.b.eq(i.b),
self.xer_ca.eq(i.xer_ca),
self.xer_so.eq(i.xer_so)]
+
+
+# TODO: replace CompALUOpSubset with CompLogicalOpSubset
+class LogicalPipeSpec:
+ regspec = (LogicalInputData.regspec, ALUOutputData.regspec)
+ opsubsetkls = CompALUOpSubset
+ def __init__(self, id_wid, op_wid):
+ self.id_wid = id_wid
+ self.op_wid = op_wid
+ self.opkls = lambda _: self.opsubsetkls(name="op")
+ self.stage = None
+ self.pipekls = SimpleHandshakeRedir
diff --git
a/src/soc/fu/logical/test/test_pipe_caller.py
b/src/soc/fu/logical/test/test_pipe_caller.py
index 4a2c09f094a4dd6f49ff613837755c9a0799a262..c14f6a08402f6a89b4aac83ce3f3763ba697c1b5 100644
(file)
--- a/
src/soc/fu/logical/test/test_pipe_caller.py
+++ b/
src/soc/fu/logical/test/test_pipe_caller.py
@@
-13,8
+13,7
@@
from soc.decoder.isa.all import ISA
from soc.fu.logical.pipeline import LogicalBasePipe
from soc.fu.logical.pipeline import LogicalBasePipe
-from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.alu.pipe_data import LogicalPipeSpec
import random
import random
@@
-181,9
+180,9
@@
class LogicalTestCase(FHDLTestCase):
self.run_tst_program(Program(lst), initial_regs)
def test_ilang(self):
self.run_tst_program(Program(lst), initial_regs)
def test_ilang(self):
- rec =
CompALUOpSubset
()
+ rec =
LogicalPipeSpec.opsubsetkls
()
- pspec =
ALU
PipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec =
Logical
PipeSpec(id_wid=2, op_wid=get_rec_width(rec))
alu = LogicalBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("logical_pipeline.il", "w") as f:
alu = LogicalBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("logical_pipeline.il", "w") as f:
@@
-204,9
+203,9
@@
class TestRunner(FHDLTestCase):
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec =
CompALUOpSubset
()
+ rec =
LogicalPipeSpec.opsubsetkls
()
- pspec =
ALU
PipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec =
Logical
PipeSpec(id_wid=2, op_wid=get_rec_width(rec))
m.submodules.alu = alu = LogicalBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
m.submodules.alu = alu = LogicalBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)