mention convenience variables

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 48dd5ef1a42f50794ed4ef5ad382e16fcda21449..5d29838f34492a0043bdf671d4e568502ed22e76 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -49,6 +49,7 @@ class TrapMainStage(PipeModBase):
         comb = m.d.comb
         op = self.i.ctx.op
 
+        # convenience variables
         a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, self.i.cia, self.i.msr
         o, msr_o, nia_o = self.o.o, self.o.msr, self.o.nia
         srr0_o, srr1_o = self.o.srr0, self.o.srr1
@@ -155,6 +156,7 @@ class TrapMainStage(PipeModBase):
 
                 with m.Else():
                     for stt, end in [(1,12), (13, 60), (61, 64)]:
+                        # TODO a_i not a
                         comb += msr_o.data[stt:end].eq(a[stt:end])
                     with m.If(a[MSR_PR]):
                             msr_o[MSR_EE].eq(1)
@@ -189,9 +191,11 @@ class TrapMainStage(PipeModBase):
                     ctrl_tmp.msr(MSR_DR) <= '1';
                 end if;
                 """
+                # TODO a_i not a, from the convenience variables
                 comb += nia_o.data.eq(br_ext(a[63:1] & 0))
                 comb += nia_o.ok.eq(1)
                 for stt, end in [(0,16), (22, 27), (31, 64)]:
+                    # TODO b_i not a, look above, the VHDL uses b_in
                     comb += msr_o.data[stt:end].eq(a[stt:end])
                 with m.If(a[MSR_PR]):
                         msr_o[MSR_EE].eq(1)