Revert "*technically* don't use a full crossbar"

This reverts commit e49a0608e702ed60db62fd36ff450828b567db42.
Doesn't reduce logic usage

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index c097357263c02dd8a61076184463c494a74a3f65..9c54e850a3136f597ec4b1279cfae1d87644f34f 100644 (file)
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -108,8 +108,8 @@ class CRMainStage(PipeModBase):
                 # Extract the two input bits from the CR
                 bit_a = Signal(reset_less=True)
                 bit_b = Signal(reset_less=True)
-                comb += bit_a.eq((1<<(31-ba) & cr) != 0)
-                comb += bit_b.eq((1<<(31-bb) & cr) != 0)
+                comb += bit_a.eq(cr_arr[ba])
+                comb += bit_b.eq(cr_arr[bb])
 
                 # Use the two input bits to look up the result in the LUT
                 bit_out = Signal(reset_less=True)
@@ -117,9 +117,7 @@ class CRMainStage(PipeModBase):
                                        Mux(bit_a, lut[3], lut[1]),
                                        Mux(bit_a, lut[2], lut[0])))
                 # Set the output to the result above
-                mask_ = Signal(32, reset_less=True)
-                comb += mask_.eq(1<<(31-bt))
-                comb += cr_o.eq(Mux(bit_out, mask_, 0) | (~mask_ & cr))
+                comb += cr_out_arr[bt].eq(bit_out)
 
             ##### mtcrf #####
             with m.Case(InternalOp.OP_MTCRF):