whoops generate core ilang not TestIssuer

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 837e1d06481011ae77c82d6575058ab156a0a830..e52aac64079f2a3abba53b589e562de8172144a3 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -310,7 +310,7 @@ class NonProductionCore(Elaboratable):
 
 
 if __name__ == '__main__':
-    dut = TestIssuer()
+    dut = NonProductionCore()
     vl = rtlil.convert(dut, ports=dut.ports())
-    with open("test_issuer.il", "w") as f:
+    with open("test_core.il", "w") as f:
         f.write(vl)