Merge branch 'master' of git.libre-soc.org:soc

diff --cc src/soc/experiment/dcache.py
index 7cb73e3438816cf0102e89a0c0cd41ad6b10ada5,4635b32bf7cb1b3cf515c1c66783c15b89862ba7..89b5207ba54b05eebb15fb2b7ce885d5c4958c35
--- 1/src/soc/experiment/dcache.py
--- 2/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@@ -993,16 -874,13 +993,20 @@@ class Dcache(Elaboratable)
  #         j := way * TLB_PTE_BITS;
  #         ptes(j + TLB_PTE_BITS - 1 downto j) := newpte;
  #     end;
 -#
 +        def write_tlb_pte(way=TLBWay(), ptes=TLBWayPtes(),
 +         newpte=TLBPte()):
 +
 +            j = Signal()
 +
 +            j = way * TLB_PTE_BITS
 +            return ptes[j:j + TLB_PTE_BITS] = newpte
 +
  # begin
  #
+ """these, because they are constants, can actually be done *as*
+    python asserts:
+    assert LINE_SIZE % ROWSIZE == 0, "line size not ...."
+ """
  #     assert LINE_SIZE mod ROW_SIZE = 0
  #      report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
  #     assert ispow2(LINE_SIZE)