attempt to split into two separate GPIO banks due to a coriolis2 compile error

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 19b217b3f354e44c95ff0a6c57cd30e3242dc6ee..41979267086168976132457e1423f239a625d4a6 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -99,7 +99,7 @@ class I2CMaster(Module, AutoCSR):
 
 
 class GPIOTristateASIC(Module, AutoCSR):
 
 
 class GPIOTristateASIC(Module, AutoCSR):

-    def __init__(self, pads):
+    def __init__(self, pads, prange=None):

         nbits     = len(pads.oe) # hack
         self._oe  = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
         self._in  = CSRStatus(nbits,  description="GPIO Input(s) Status.")
         nbits     = len(pads.oe) # hack
         self._oe  = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
         self._in  = CSRStatus(nbits,  description="GPIO Input(s) Status.")


@@ -116,7 +116,9 @@ class GPIOTristateASIC(Module, AutoCSR):
 
         self.comb += _pads.oe.eq(self._oe.storage)
         self.comb += _pads.o.eq(self._out.storage)
 
         self.comb += _pads.oe.eq(self._oe.storage)
         self.comb += _pads.o.eq(self._out.storage)

-        for i in range(nbits):
+        if prange is None:
+            prange = range(nbits)
+        for i in prange:

             self.specials += MultiReg(_pads.i[i], self._in.status[i])
 
 # SDCard PHY IO -------------------------------------------------------
             self.specials += MultiReg(_pads.i[i], self._in.status[i])
 
 # SDCard PHY IO -------------------------------------------------------


@@ -328,7 +330,7 @@ class LibreSoCSim(SoCCore):
             cpu_type                 = "microwatt",
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,
             cpu_type                 = "microwatt",
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,

-            #bus_data_width           = 64,
+            bus_data_width           = 64,

             csr_address_width        = 14, # limit to 0x8000
             cpu_variant              = variant,
             csr_data_width            = 8,
             csr_address_width        = 14, # limit to 0x8000
             cpu_variant              = variant,
             csr_data_width            = 8,


@@ -441,9 +443,12 @@ class LibreSoCSim(SoCCore):
 
         # GPIOs (bi-directional)
         gpio_core_pads = self.cpu.cpupads['gpio']
 
         # GPIOs (bi-directional)
         gpio_core_pads = self.cpu.cpupads['gpio']

-        self.submodules.gpio = GPIOTristateASIC(gpio_core_pads)
+        self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8))

         self.add_csr("gpio")
 
         self.add_csr("gpio")
 

+        self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8,16))
+        self.add_csr("gpio1")
+

         # SPI Master
         print ("cpupadkeys", self.cpu.cpupads.keys())
         self.submodules.spimaster = SPIMaster(
         # SPI Master
         print ("cpupadkeys", self.cpu.cpupads.keys())
         self.submodules.spimaster = SPIMaster(