whoops merged the two write-ports for RT and RA-with-update

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index ade46bafc9f8a07a0cd59d577c00b582c7417259..7d98bb9b097332a0bb71364784deba1968651a91 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -776,7 +776,7 @@ class NonProductionCore(ControlBase):
                 name = "%s_%s_%s_%d" % (funame, regfile, regname, idx)
                 # get (or set up) a write-latched copy of write register number
                 write = Signal.like(_write, name="write_"+name)
-                rname = "%s_%s_%s" % (funame, regfile, regname)
+                rname = "%s_%s_%s_%d" % (funame, regfile, regname, idx)
                 if rname not in fu.wr_latches:
                     wrl = Signal.like(_write, name="wrlatch_"+rname)
                     fu.wr_latches[rname] = write